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&qspi_clkqspi-cs0-state!gpio90&qspi_csqspi-cs1-state!gpio89&qspi_csqspi-data0-state!gpio91 &qspi_dataqspi-data1-state!gpio92 &qspi_dataqspi-data23-state!gpio93gpio94 &qspi_dataqup-i2c0-default-state !gpio0gpio1&qup0U>qup-i2c1-default-state!gpio17gpio18&qup1UCqup-i2c2-default-state!gpio27gpio28&qup2UFqup-i2c3-default-state!gpio41gpio42&qup3UIqup-i2c4-default-state!gpio89gpio90&qup4ULqup-i2c5-default-state!gpio85gpio86&qup5UOqup-i2c6-default-state!gpio45gpio46&qup6URqup-i2c7-default-state!gpio93gpio94&qup7UUqup-i2c8-default-state!gpio65gpio66&qup8UYqup-i2c9-default-state !gpio6gpio7&qup9U]qup-i2c10-default-state!gpio55gpio56&qup10U`qup-i2c11-default-state!gpio31gpio32&qup11Ucqup-i2c12-default-state!gpio49gpio50&qup12Ufqup-i2c13-default-state!gpio105gpio106&qup13Uiqup-i2c14-default-state!gpio33gpio34&qup14Ulqup-i2c15-default-state!gpio81gpio82&qup15Uoqup-spi0-default-state!gpio0gpio1gpio2gpio3&qup0UAqup-spi1-default-state!gpio17gpio18gpio19gpio20&qup1UDqup-spi2-default-state!gpio27gpio28gpio29gpio30&qup2UGqup-spi3-default-state!gpio41gpio42gpio43gpio44&qup3UJqup-spi4-default-state!gpio89gpio90gpio91gpio92&qup4UMqup-spi5-default-state!gpio85gpio86gpio87gpio88&qup5UPqup-spi6-default-state!gpio45gpio46gpio47gpio48&qup6USqup-spi7-default-state!gpio93gpio94gpio95gpio96&qup7UVqup-spi8-default-state!gpio65gpio66gpio67gpio68&qup8U[qup-spi9-default-state!gpio6gpio7gpio4gpio5&qup9U^qup-spi10-default-state!gpio55gpio56gpio53gpio54&qup10Uaqup-spi11-default-state!gpio31gpio32gpio33gpio34&qup11Udqup-spi12-default-state!gpio49gpio50gpio51gpio52&qup12Ugqup-spi13-default-state !gpio105gpio106gpio107gpio108&qup13Ujqup-spi14-default-state!gpio33gpio34gpio31gpio32&qup14Umqup-spi15-default-state!gpio81gpio82gpio83gpio84&qup15Upqup-uart0-default-stateUBtx-pins!gpio2&qup0rx-pins!gpio3&qup0qup-uart1-default-stateUEtx-pins!gpio19&qup1rx-pins!gpio20&qup1qup-uart2-default-stateUHtx-pins!gpio29&qup2rx-pins!gpio30&qup2qup-uart3-default-stateUKtx-pins!gpio43&qup3rx-pins!gpio44&qup3qup-uart3-4pin-statects-pins!gpio41&qup3rts-tx-pins!gpio42gpio43&qup3rx-pins!gpio44&qup3qup-uart4-default-stateUNtx-pins!gpio91&qup4rx-pins!gpio92&qup4qup-uart5-default-stateUQtx-pins!gpio87&qup5rx-pins!gpio88&qup5qup-uart6-default-stateUTtx-pins!gpio47&qup6rx-pins!gpio48&qup6qup-uart6-4pin-statects-pins!gpio45&qup6Krts-tx-pins!gpio46gpio47&qup6<Zrx-pins!gpio48&qup6/qup-uart7-default-stateUWtx-pins!gpio95&qup7rx-pins!gpio96&qup7qup-uart8-default-stateU\tx-pins!gpio67&qup8rx-pins!gpio68&qup8qup-uart9-default-stateU_tx-pins!gpio4&qup9rx-pins!gpio5&qup9qup-uart10-default-stateUbtx-pins!gpio53&qup10rx-pins!gpio54&qup10qup-uart11-default-stateUetx-pins!gpio33&qup11rx-pins!gpio34&qup11qup-uart12-default-stateUhtx-pins!gpio51&qup0rx-pins!gpio52&qup0qup-uart13-default-stateUktx-pins!gpio107&qup13rx-pins!gpio108&qup13qup-uart14-default-stateUntx-pins!gpio31&qup14rx-pins!gpio32&qup14qup-uart15-default-stateUqtx-pins!gpio83&qup15rx-pins!gpio84&qup15quat-mi2s-sleep-state!gpio58gpio59&gpio<Kquat-mi2s-active-state!gpio58gpio59 &qua_mi2s<Zgquat-mi2s-sd0-sleep-state!gpio60&gpio<Kquat-mi2s-sd0-active-state!gpio60 &qua_mi2s<Zquat-mi2s-sd1-sleep-state!gpio61&gpio<Kquat-mi2s-sd1-active-state!gpio61 &qua_mi2s<Zquat-mi2s-sd2-sleep-state!gpio62&gpio<Kquat-mi2s-sd2-active-state!gpio62 &qua_mi2s<Zquat-mi2s-sd3-sleep-state!gpio63&gpio<Kquat-mi2s-sd3-active-state!gpio63 &qua_mi2s<Zsdc2-clk-state !sdc2_clkZ<U�sdc2-cmd-state !sdc2_cmd/<U�sdc2-data-state !sdc2_data/<U�sd-card-det-n-state!gpio126&gpio/U�thinq-key-default-state!gpio89&gpio</U�remoteproc@40800002qcom,sdm845-mss-pil �H kqdsp6rmbLa �����0uwdogfatalreadyhandoverstop-ackshutdown-ack@i;$;';;%;(;&;@.2�ifacebusmemgpll0_msssnoc_aximnoc_axiprngxo�0���stop��� �mss_restartpdc_resets�0P@�::: �cxmxmss�okay8�qcom/sdm845/judyln/mba.mbnqcom/sdm845/judyln/modem.mbnmba��mpss��metadata��glink-edge ���modem��2 clock-controller@50900002qcom,sdm845-gpucc� �%��i.;; 8�bi_tcxogcc_gpu_gpll0_clk_srcgcc_gpu_gpll0_div_clk_srcU�remoteproc@5c000002qcom,sdm845-slpi-pas��@@a�����#uwdogfatalreadyhandoverstop-acki.�xo�0�::�lcxlmx�����stop �disabledglink-edge ���dsps��2fastrpc 2qcom,fastrpcfastrpcglink-apps-dsp�sdsp]��� compute-cb@02qcom,fastrpc-compute-cb�stm@6002000 2arm,coresight-stmarm,primecell � (kstm-basestm-stimulus-basei0 �apb_pclkout-portsportendpoint��U�funnel@6041000+2arm,coresight-dynamic-funnelarm,primecell�i0 �apb_pclkout-portsportendpoint��U�in-ports port@7�endpoint��U�funnel@6043000+2arm,coresight-dynamic-funnelarm,primecell�0i0 �apb_pclkout-portsportendpoint��U�in-ports port@5�endpoint��U�funnel@6045000+2arm,coresight-dynamic-funnelarm,primecell�Pi0 �apb_pclkout-portsportendpoint��U�in-ports port@0�endpoint��U�port@2�endpoint��U�replicator@6046000/2arm,coresight-dynamic-replicatorarm,primecell�`i0 �apb_pclkout-portsportendpoint��U�in-portsportendpoint��U�etf@6047000 2arm,coresight-tmcarm,primecell�pi0 �apb_pclkout-portsportendpoint��U�in-portsportendpoint��U�etr@6048000 2arm,coresight-tmcarm,primecell��i0 �apb_pclk�in-portsportendpoint��U�etm@7040000"2arm,coresight-etm4xarm,primecell�9i0 �apb_pclk�out-portsportendpoint��U�etm@7140000"2arm,coresight-etm4xarm,primecell�9i0 �apb_pclk�out-portsportendpoint��U�etm@7240000"2arm,coresight-etm4xarm,primecell�$9i0 �apb_pclk�out-portsportendpoint��U�etm@7340000"2arm,coresight-etm4xarm,primecell�49i0 �apb_pclk�out-portsportendpoint��U�etm@7440000"2arm,coresight-etm4xarm,primecell�D9i0 �apb_pclk�out-portsportendpoint��U�etm@7540000"2arm,coresight-etm4xarm,primecell�T9 i0 �apb_pclk�out-portsportendpoint��U�etm@7640000"2arm,coresight-etm4xarm,primecell�d9!i0 �apb_pclk�out-portsportendpoint��U�etm@7740000"2arm,coresight-etm4xarm,primecell�t9"i0 �apb_pclk�out-portsportendpoint��U�funnel@7800000+2arm,coresight-dynamic-funnelarm,primecell��i0 �apb_pclkout-portsportendpoint��U�in-ports port@0�endpoint��U�port@1�endpoint��U�port@2�endpoint��U�port@3�endpoint��U�port@4�endpoint��U�port@5�endpoint��U�port@6�endpoint��U�port@7�endpoint��U�funnel@7810000+2arm,coresight-dynamic-funnelarm,primecell��i0 �apb_pclkout-portsportendpoint��U�in-portsportendpoint��U�mmc@8804000$2qcom,sdm845-sdhciqcom,sdhci-msm-v5��@���uhc_irqpwr_irqi;h;i.�ifacecorexo V3��:���okay �w~DdefaultR��������opp-table2operating-points-v2U�opp-9600000��|�#opp-19200000�$��$opp-100000000����%opp-201500000� �`�&spi@88df0002qcom,sdm845-qspiqcom,qspi-v1��� V3`  �Ri;�;� �ifacecore�:�� �disabledslim-ngd@171c00002qcom,slim-ngd-v2.1.0�� ��\��arxtx V3  �disabledlmh@17d708002qcom,sdm845-lmh�� �!����q$:s��U�lmh@17d788002qcom,sdm845-lmh�׈ � ����q$:s��U�phy@88e2000(2qcom,sdm845-qusb2-phyqcom,qusb2-v2-phy�� �okay�i;�. �cfg_ahbref�;Z�fz��q�����U�phy@88e3000(2qcom,sdm845-qusb2-phyqcom,qusb2-v2-phy��0 �disabled�i;�. �cfg_ahbref�; Z�U�phy@88e80002qcom,sdm845-qmp-usb3-dp-phy���0�okay(i;�;�;�;�;�"�auxrefcom_auxusb3_pipecfg_ahb�;; �phycommon%��w{�zU�ports port@0�endpointport@1�endpoint��U�port@2�endpoint��U�phy@88eb0002qcom,sdm845-qmp-usb3-uni-phy���(i;�;�;�;�;��auxcfg_ahbrefcom_auxpipeBusb3_uni_phy_pipe_clk_src%��;; �phyphy_phy �disabledU�usb@a6f88002qcom,sdm845-dwc3qcom,dwc3� o��okay ��(i; ;�;;�;�#�cfg_noccoreifacesleepmock_utmi�;�;�$��рDa��� ��<upwr_evenths_phy_irqdp_hs_phy_irqdm_hs_phy_irqss_phy_irq�;�;0�X=)1usb-ddrapps-usbusb@a600000 2snps,dwc3� `� �� V3@�  ' ����usb2-phyusb3-phy Fperipheralports port@0�endpointport@1�endpoint��U�usb@a8f88002qcom,sdm845-dwc3qcom,dwc3� �� �disabled ��(i; ;�;;�;�#�cfg_noccoreifacesleepmock_utmi�;�;�$��рDa��� � �<upwr_evenths_phy_irqdp_hs_phy_irqdm_hs_phy_irqss_phy_irq�;�;0�X=*1usb-ddrapps-usbusb@a800000 2snps,dwc3� �� �� V3`�  '����usb2-phyusb3-phyvideo-codec@aa000002qcom,sdm845-venus-v2� �� �� ����:�venusvcodec0vcodec1cx��8i� �� ����A�coreifacebusvcodec0_corevcodec0_busvcodec1_corevcodec1_busV3�3���0��=+1video-memcpu-cfg �disabledvideo-core02venus-decodervideo-core12venus-encoderopp-table2operating-points-v2U�opp-100000000����#opp-200000000� ���$opp-320000000���%opp-380000000��W�&opp-444000000�v��'opp-533000097�����clock-controller@ab000002qcom,sdm845-videocc� �i.�bi_tcxo%��U�camss@acb30002qcom,sdm845-camss�� �0 ˠ ̀ �P �` �p ƀ ��@ �`@ �@@Ekcsid0csid1csid2csiphy0csiphy1csiphy2csiphy3vfe0vfe1vfe_litex�����������Eucsid0csid1csid2csiphy0csiphy1csiphy2csiphy3vfe0vfe1vfe_lite���� i�� � �%�&�,�-�2�3�� � �� �������;;�R�S�!�"�$�#�(�)�+�*�/�1�0��camnoc_axicpas_ahbcphy_rx_srccsi0csi0_srccsi1csi1_srccsi2csi2_srccsiphy0csiphy0_timercsiphy0_timer_srccsiphy1csiphy1_timercsiphy1_timer_srccsiphy2csiphy2_timercsiphy2_timer_srccsiphy3csiphy3_timercsiphy3_timer_srcgcc_camera_ahbgcc_camera_axislow_ahb_srcsoc_ahbvfe0_axivfe0vfe0_cphy_rxvfe0_srcvfe1_axivfe1vfe1_cphy_rxvfe1_srcvfe_litevfe_lite_cphy_rxvfe_lite_src0V333 3  �disabledports port@0�port@1�port@2�port@3�cci@ac4a000!2qcom,sdm845-cciqcom,msm8996-cci � Ġ@ ����0i��S�R� ��5�camnoc_axisoc_ahbslow_ahb_srccpas_ahbccicci_src���Ĵ<4`DdefaultsleepR�� N�� �disabledi2c-bus@0�2B@ i2c-bus@1�2B@ clock-controller@ad000002qcom,sdm845-camcc� �%��i.�bi_tcxoU�display-subsystem@ae000002qcom,sdm845-mdss� �kmdss��i��  �ifacecore �S��0���1mdp0-memmdp1-memV3�3 � �disabled �U�display-controller@ae010002qcom,sdm845-dpu � �� �  kmdpvbif(i;��� ��gcc-busifacebuscorevsync��$����:��ports port@0�endpoint��U�port@1�endpoint��U�port@2�endpoint��U�opp-table2operating-points-v2U�opp-19200000�$��#opp-171428571� 7���$opp-344000000���&opp-430000000��G��'displayport-controller@ae90000 �disabled2qcom,sdm845-dpP� � � � �  ��� (i��� �"�%;�core_ifacecore_auxctrl_linkctrl_link_ifacestream_pixel��!�& X�����dp���:ports port@0�endpoint��U�port@1�endpoint��U�opp-table2operating-points-v2U�opp-162000000� ���$opp-270000000�߀�%opp-540000000� /��&opp-810000000�0G���'dsi@ae94000(2qcom,sdm845-dsi-ctrlqcom,mdss-dsi-ctrl� �@ kdsi_ctrl��0i������$�bytebyte_intfpixelcoreifacebus��� X�����:�� �disabled ports port@0�endpoint��U�port@1�endpointphy@ae944002qcom,dsi-phy-10nm0� �D �F� �J�kdsi_phydsi_phy_lanedsi_pll%�i�. �ifaceref �disabledU�dsi@ae96000(2qcom,sdm845-dsi-ctrlqcom,mdss-dsi-ctrl� �` kdsi_ctrl��0i���� ��$�bytebyte_intfpixelcoreifacebus��� X�����:�� �disabled ports port@0�endpoint��U�port@1�endpointphy@ae964002qcom,dsi-phy-10nm0� �d �f� �jkdsi_phydsi_phy_lanedsi_pll%�i�. �ifaceref �disabledU�gpu@50000002qcom,adreno-630.2qcom,adreno � �kkgsl_3d0_reg_memorycx_mem �,V��� o���1gfx-mem�okayU�opp-table2operating-points-v2U�opp-710000000�*Q�� x��n�opp-675000000�(;�� x��n�opp-596000000�#�= x@�^��opp-520000000��� x�^��opp-414000000��#� x��>�opp-342000000�b�� x��)��opp-257000000�Q�@ x@�%�zap-shader�� �qcom/sdm845/judyln/a630_zap.mbniommu@504000022qcom,sdm845-smmu-v2qcom,adreno-smmuqcom,smmu-v2� � �x���lmnopqrsi;!; �busiface��U�gmu@506a000&2qcom,adreno-gmu-630.2qcom,adreno-gmu0�� ( Hkgmugmu_pdcgmu_pdc_seq�01uhfigmu i��;;!�gmucxoaximemnoc����cxgxV��� �disabledU�opp-table2operating-points-v2U�opp-400000000�ׄ x�opp-200000000� �� x0clock-controller@af000002qcom,sdm845-dispcc� �Hi.;;��������bi_tcxogcc_disp_gpll0_clk_srcgcc_disp_gpll0_div_clk_srcdsi0_phy_pll_out_byteclkdsi0_phy_pll_out_dsiclkdsi1_phy_pll_out_byteclkdsi1_phy_pll_out_dsiclkdp_link_clk_divsel_tendp_vco_divided_clk_src_mux%�� �disabledU�interrupt-controller@b2200002qcom,sdm845-pdcqcom,pdc� "$ ��^^asv��U�reset-controller@b2e00002qcom,sdm845-pdc-global� .�U�thermal-sensor@c263000 2qcom,sdm845-tsensqcom,tsens-v2 � &0� " � � ���uuplowcritical �U�thermal-sensor@c265000 2qcom,sdm845-tsensqcom,tsens-v2 � &P� "0� ����uuplowcritical �U�reset-controller@c2a00002qcom,sdm845-aoss-cc� *�U�power-management@c300000#2qcom,sdm845-aoss-qmpqcom,aoss-qmp� 0 ���2%U0cx�ebi�sram@c3f00002qcom,sdm845-rpmh-stats� ?spmi@c4400002qcom,spmi-pmic-arbP� D ``p @�`kcorechnlsobsrvrintrcnfg uperiph_irq ��� � ��pmic@02qcom,pm8998qcom,spmi-pmic� pon@8002qcom,pm8998-pon� � �pwrkey2qcom,pm8941-pwrkey� = / tresin2qcom,pm8941-resin� = /�okay rtemp-alarm@24002qcom,spmi-temp-alarm�$�$ � !thermal �U�charger@2800*2qcom,pm8998-coincellqcom,pm8941-coincell�( �disabledadc@31002qcom,spmi-adc-rev2�1�1  2U�channel@6� �die_tempadc-tm@34002qcom,spmi-adc-tm-hc�4�4 �  �disabledrtc@60002qcom,pm8941-rtc�`a krtcalarm�agpio@c000 2qcom,pm8998-gpioqcom,spmi-gpio��������U�vol-up-active-state!gpio6&normal D/ QU�pmic@12qcom,pm8998qcom,spmi-pmic� pmic@22qcom,pmi8998qcom,spmi-pmic� charger@10002qcom,pmi8998-charger�@�-uusb-pluginbat-ovwdog-barkusbin-icl-change �� !usbin_iusbin_v �disabledgpio@c000!2qcom,pmi8998-gpioqcom,spmi-gpio��������U�adc@45002qcom,pmi8998-rradc�E 2U�pmic@32qcom,pmi8998qcom,spmi-pmic� labibb2qcom,pmi8998-lab-ibbibb ��� usc-errocpUlab ��� usc-errocpUpwm2qcom,pmi8998-lpg  e �disabledled-controller@d300+2qcom,pmi8998-flash-ledqcom,spmi-flash-led�� �disabledleds@d8002qcom,pmi8998-wled��� ��� uovpshort �backlight �disabledsram@146bf000#2qcom,sdm845-imemsysconsimple-mfd�k� �k�pil-reloc@94c2qcom,pil-reloc-info� L�iommu@15000000!2qcom,sdm845-smmu-500arm,mmu-500� � � �A`abcdefghijklmnopqrstuv������������;<=>?@ABCDEFGHIJKLMNOPQRSTUVWU3tbu@150c50002qcom,sdm845-tbu� P�~=�; p3tbu@150c90002qcom,sdm845-tbu� ��~=�;  p3tbu@150cd0002qcom,sdm845-tbu� ���� �;  p3tbu@150d10002qcom,sdm845-tbu� ��� �;  p3 tbu@150d50002qcom,sdm845-tbu� P��� �;  p3tbu@150d90002qcom,sdm845-tbu� ��~= p3tbu@150dd0002qcom,sdm845-tbu� ��~=�; p3tbu@150e10002qcom,sdm845-tbu�i;�~=�; p3clock-controller@170140002qcom,sdm845-lpasscc �@�0 kccqdsp6ss% �disabledinterconnect@179000002qcom,sdm845-gladiator-noc��Ѐ+tUwatchdog@17980000#2qcom,apss-wdt-sdm845qcom,kpss-wdt��i7 �mailbox@179900002qcom,sdm845-apss-shared�� �U2rsc@179c0000 �apps_rsc2qcom,rpmh-rsc0����kdrv-0drv-1drv-2$� �  � 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interrupt-parent#address-cells#size-cellsmodelcompatiblei2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8i2c9i2c10i2c11i2c12i2c13i2c14i2c15spi0spi1spi2spi3spi4spi5spi6spi7spi8spi9spi10spi11spi12spi13spi14spi15rangesregwidthheightstrideformatlab-supplyibb-supply#clock-cellsclock-frequencyclock-output-namesphandledevice_typeclocksenable-methodcapacity-dmips-mhzdynamic-power-coefficientqcom,freq-domainoperating-points-v2interconnectspower-domainspower-domain-names#cooling-cellsnext-level-cachecache-levelcache-unifiedcpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uslocal-timer-stopopp-sharedopp-hzopp-peak-kBpsrequired-oppsinterrupts#power-domain-cellsdomain-idle-statesno-maphwlocksalloc-rangessizealignmentreusableqcom,client-idqcom,vmidinterrupts-extendedinterrupt-namesclock-namesmemory-regionqcom,qmpqcom,smem-statesqcom,smem-state-namesstatusfirmware-namelabelqcom,remote-pidmboxesqcom,glink-channelsqcom,domainqcom,intentsqcom,protection-domain#sound-dai-cellsiommusqcom,non-secure-domainqcom,smemqcom,local-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#reset-cellsprotected-clocksbits#dma-cellsdma-channelsdma-channel-maskinterconnect-namespinctrl-namespinctrl-0dmasdma-namesreg-nameslinux,pci-domainbus-rangenum-lanesinterrupt-map-maskinterrupt-mapiommu-mapresetsreset-namesphysphy-names#phy-cellsassigned-clocksassigned-clock-rates#interconnect-cellsqcom,bcm-voterslanes-per-directionreset-gpiosvcc-supplyvcc-max-microampvdda-phy-supplyvdda-pll-supplyqcom,eeqcom,controlled-remotelyqcom,gsi-loader#hwlock-cellsgpio-controller#gpio-cellsgpio-rangeswakeup-parentgpio-reserved-rangespinsfunctionbias-pull-updrive-strengthbias-pull-downbias-disableoutput-highqcom,halt-regsqcom,vmidsremote-endpointarm,scatter-gatherarm,coresight-loses-context-with-cpucd-gpiosvmmc-supplyvqmmc-supplycpusqcom,lmh-temp-arm-millicelsiusqcom,lmh-temp-low-millicelsiusqcom,lmh-temp-high-millicelsiusnvmem-cellsvdd-supplyvdda-phy-dpdm-supplyqcom,imp-res-offset-valueqcom,hstx-trim-valueqcom,preemphasis-levelqcom,preemphasis-widthorientation-switchsnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,parkmode-disable-ss-quirkdr_modepinctrl-1assigned-clock-parentsqcom,gmuopp-level#iommu-cells#global-interruptsqcom,pdc-ranges#qcom,sensors#thermal-sensor-cellsqcom,channelmode-bootloadermode-recoverydebouncelinux,codeio-channelsio-channel-names#io-channel-cellsinput-enableqcom,drive-strength#pwm-cellsqcom,stream-id-range#mbox-cellsqcom,tcs-offsetqcom,drv-idqcom,tcs-configqcom,pmic-idvdd-s1-supplyvdd-s2-supplyvdd-s3-supplyvdd-s4-supplyvdd-s5-supplyvdd-s6-supplyvdd-s7-supplyvdd-s8-supplyvdd-s9-supplyvdd-s10-supplyvdd-s11-supplyvdd-s12-supplyvdd-s13-supplyvdd-l1-l27-supplyvdd-l2-l8-l17-supplyvdd-l3-l11-supplyvdd-l4-l5-supplyvdd-l6-supplyvdd-l7-l12-l14-l15-supplyvdd-l9-supplyvdd-l10-l23-l25-supplyvdd-l13-l19-l21-supplyvdd-l16-l28-supplyvdd-l18-l22-supplyvdd-l20-l24-supplyvdd-l26-supplyvin-lvs-1-2-supplyregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-always-onvdd-bob-supplyregulator-allow-bypassmsi-controller#msi-cellsnum-channelsqcom,num-eesframe-number#freq-domain-cellspolling-delay-passivethermal-sensorstemperaturehysteresistripcooling-deviceregulator-nameregulator-boot-onvin-supply