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#address-cells#size-cellsmodelcompatiblestdout-pathgpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2i2c3mmc0mmc1mmc2serial0serial1serial2serial3serial4serial5serial6spi0spi1spi2spi3usb0usb1usb2entry-methodarm,psci-suspend-paramlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usphandledevice_typeregclock-frequencyclock-latencyclockscpu-idle-statesoperating-points-v2#cooling-cellsnvmem-cellsnvmem-cell-namescpu-supplyopp-sharedopp-hzopp-microvoltclock-latency-nsopp-supported-hwopp-suspend#clock-cellsclock-output-namesclock-names#phy-cellspower-domainsinterrupt-parentinterruptsinterrupt-affinityremote-endpointarm,cpu-registers-not-fw-configuredrangescpu#interrupt-cellsinterrupt-controllergpio-controller#gpio-cellsgpio-rangesstatusfsl,input-selfsl,phyfsl,pins#mux-control-cellsmux-reg-masksmux-controlsregulator-nameregulator-min-microvoltregulator-max-microvoltanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitfsl,tempmonregmaplinux,keycodewakeup-source#reset-cells#power-domain-cellspower-supply#io-channel-cells#pwm-cellsphy-supplyresetspinctrl-namespinctrl-0cs-gpiosspi-max-frequencyassigned-clocksassigned-clock-parents#sound-dai-cellsdma-namesdmasfsl,stop-moderegulator-boot-onregulator-always-onregulator-ramp-delaycurrent-speedzii,eeprom-name#mbox-cellsfsl,mu-side-bfsl,usbphyfsl,usbmiscphy-clkgate-delay-usphy_typedr_mode#index-cellsbus-widthfsl,tuning-stepfsl,tuning-start-tapno-1-8-vno-sdiokeep-power-in-suspendnon-removableno-sdreg-names#dma-cellsfsl,sdma-ram-script-nameinterrupt-namesfsl,num-tx-queuesfsl,num-rx-queuesassigned-clock-ratesphy-modephy-handlereset-gpiosdisable-over-currentdma-channelsarm,primecell-periphidbus-rangenum-lanesinterrupt-map-maskinterrupt-mapfsl,max-link-speedreset-namesfsl,imx7d-pcie-phylabellinux,default-trigger