� ��)8&�(�&H%xlnx,zynq-zc770-xm011xlnx,zynq-7000&Xilinx ZC770 XM011 boardcpuscpu@0arm,cortex-a9,cpu8<C�Q] ,+B@B@ncpu@1arm,cortex-a9,cpu8<nfpga-full fpga-regionvpmu@f8891000arm,cortex-a9-pmu��8����0fixedregulatorregulator-fixed�VCCPINT�B@�B@��nreplicator arm,coresight-static-replicator<./apb_pclkdbg_trcdbg_apbout-portsport@08endpointn port@18endpointn in-portsportendpointn axi simple-bus�adc@f8007100xlnx,zynq-xadc-1.00.a8�q  ��< can@e0008000xlnx,zynq-can-1.0#okay<$ can_clkpclk8�� ��*@8@can@e0009000xlnx,zynq-can-1.0 #disabled<% can_clkpclk8�� �3�*@8@gpio@e000a000xlnx,zynq-gpio-1.0F<*Rbw� �8��i2c@e0004000cdns,i2c-r1p10 #disabled<&� ���8�@i2c@e0005000cdns,i2c-r1p10#okay<'� �0��8�Peeprom@52 atmel,24c028Rinterrupt-controller@f8f01000arm,cortex-a9-gicwb8����ncache-controller@f8f02000arm,pl310-cache8��  � � ���memory-controller@f8006000xlnx,zynq-ddrc-a058�`serial@e0000000xlnx,xuartpscdns,uart-r1p8 #disabled<(uart_clkpclk8� �serial@e0001000xlnx,xuartpscdns,uart-r1p8#okay<)uart_clkpclk8� �2spi@e0006000xlnx,zynq-spi-r1p68�`#okay� �<" ref_clkpclk��spi@e0007000xlnx,zynq-spi-r1p68�p #disabled� �1<# ref_clkpclkspi@e000d000xlnx,zynq-qspi-1.08��� �< + ref_clkpclk #disabledethernet@e000b000xlnx,zynq-gemcdns,gem8�� #disabled �< pclkhclktx_clkethernet@e000c000xlnx,zynq-gemcdns,gem8�� #disabled �-<pclkhclktx_clkmemory-controller@e000e000!arm,pl353-smc-r2p1arm,primecell8�� #disabledmemclkapb_pclk< ,0���nand-controller@0,0arm,pl353-nand-r2p1 8 #disabledmmc@e0100000arasan,sdhci-8.9a #disabledclk_xinclk_ahb< � �8�mmc@e0101000arasan,sdhci-8.9a #disabledclk_xinclk_ahb<!� �/8�slcr@f8000000!xlnx,zynq-slcrsysconsimple-mfd8�nclkc@100�xlnx,ps7-clkc�jarmpllddrplliopllcpu_6or4xcpu_3or2xcpu_2xcpu_1xddr2xddr3xdcilqspismcpcapgem0gem1fclk0fclk1fclk2fclk3can0can1sdio0sdio1uart0uart1spi0spi1dmausb0_aperusb1_apergem0_apergem1_apersdio0_apersdio1_aperspi0_aperspi1_apercan0_apercan1_aperi2c0_aperi2c1_aperuart0_aperuart1_apergpio_aperlqspi_apersmc_aperswdtdbg_trcdbg_apb8nrstc@200xlnx,zynq-reset8H!pinctrl@700xlnx,pinctrl-zynq8!dma-controller@f8003000arm,pl330arm,primecell8�0�l� ()*+(< apb_pclkdevcfg@f8007000xlnx,zynq-devcfg-1.08�p� �< ref_clk!ntimer@f8f00200arm,cortex-a9-global-timer8��  � �<timer@f8001000�$�    cdns,ttc<8�timer@f8002000�$�%&' cdns,ttc<8� timer@f8f00600� � arm,cortex-a9-twd-timer8�� <usb@e0002000"xlnx,zynq-usb-2.20achipidea,usb2 #disabled<� �8� 3ulpiusb@e0003000"xlnx,zynq-usb-2.20achipidea,usb2#okay<� �,8�03ulpi