Package: verilator-4.032 Version: 4.032-1 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 14292 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.032_4.032-1_amd64.deb Size: 3178150 MD5sum: 246b7fcb849b6873f6014286b3bf4a4d SHA1: d5370338e436840850037241c9413c0453941196 SHA256: 36f541ea781334285a9b499e63b0785b371b800fef06824777e3b421687d962a Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. 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Package: verilator-4.040 Version: 4.040-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15522 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.040_4.040-0_amd64.deb Size: 3471346 MD5sum: a45b916bd28c3a160c5ac5ba51d79c5c SHA1: d3c1c2140f5ee2ffdaaac08a50819a83d3a569c2 SHA256: fb339ef8f2039082c8589f4641c5d9dfb52289de93c01c304b70fe38d1cda4da Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. 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Package: verilator-4.104 Version: 4.104-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15354 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.104_4.104-0_amd64.deb Size: 3406298 MD5sum: 2822a29d94ada772af7bbac18add11cb SHA1: c20e44ad9b9b6103ee94c134eabd9550d0701a65 SHA256: f27bceadce0e2e4704a9911d579185ead124443ce330b078939cc1d72cb2674f Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.106 Version: 4.106-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15439 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.106_4.106-0_amd64.deb Size: 3424790 MD5sum: 4c4cf7cea4522dfdeb576f85e54e2885 SHA1: e32a6c59420478c29658935a01a721af55676465 SHA256: c3760c60b5254a01ac3aa92f6fb87a95209dce41c558369e4a157229107bd586 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.108 Version: 4.108-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15557 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.108_4.108-0_amd64.deb Size: 3453514 MD5sum: 51bbab920d88b57ae73fbf773627a188 SHA1: 8e90ccf3c87a1aef284923a77c4d6a8cd8278b4a SHA256: 7c4b53cee0e4bc70c3eb53901a60964cb9531387b25340a43c6311294e96601f Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.110 Version: 4.110-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15622 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.110_4.110-0_amd64.deb Size: 3467794 MD5sum: 5aa3c8415ab8f83f31839f89a38ec4dc SHA1: 63be47001a7cabc212c49e03db94a15902293151 SHA256: fcdf2cd44b1045fb1cd593c77858ff127cd21a1840d99a2dcabbe658adf9516f Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.200 Version: 4.200-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15660 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.200_4.200-0_amd64.deb Size: 3489592 MD5sum: 4ebf9f83016bfbae67e8ffd1646bffe6 SHA1: fb2cd7e3e067a94f4d16e2e7d1d6058b1ae1f8e1 SHA256: ec9b9bc829561d1e76abd1be3c428a3a850f1e2f63d10afa0f941bd0e1d895cb Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.202 Version: 4.202-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 15590 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.202_4.202-0_amd64.deb Size: 3395444 MD5sum: e1a2d5e1eba86230cacc8509ca988f4e SHA1: 2780e6949fd703e106292a6663a448f0f757e5c1 SHA256: a6b5402850208261cc420d4befd99864e1a7433f90f3fb46f48b30ca6735ac43 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.210 Version: 4.210-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 16922 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.210_4.210-0_amd64.deb Size: 3841720 MD5sum: 7a7e75a256cce910b95b63d9c95f7d07 SHA1: 4d60bab5382a328a26ba9d5a2b7893ae8d601972 SHA256: 9f38a62ca27d98a2fd7e99debbdacf3bd89a448db1299cec38f181f47411b12e Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.212 Version: 4.212-0 Architecture: amd64 Maintainer: Philipp Wagner Installed-Size: 17078 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.212_4.212-0_amd64.deb Size: 3755398 MD5sum: 49649d85248fa8e6627ac05a561cf128 SHA1: c93c7c0da9cefcb226a559fefff2f207bab6fe4d SHA256: 57319beac7200e2c010d5ef8e34b550905db954630938fcae2f408f76ffc803f Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.