Package: openocd-0.11.0 Version: 0.11.0-1 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 5224 Depends: libc6 (>= 2.15), libcapstone3 (>= 3.0.0), libftdi1-2 (>= 1.2), libgpiod1 (>= 1.0), libhidapi-hidraw0 (>= 0.8.0~rc1+git20140201.3a66d4e+dfsg), libjim0.77 (>= 0.73), libusb-0.1-4 (>= 2:0.1.12), libusb-1.0-0 (>= 2:1.0.16) Filename: ./amd64/openocd-0.11.0_0.11.0-1_amd64.deb Size: 1514172 MD5sum: 4bc70b6de86dc9f4ecdd7dfe1f0b47aa SHA1: d461459a96c295126d2f1101b736daf9b895bd91 SHA256: 3b84f66f0915f4daf396db738bb82a72800bc7e214eee040694f90c9325461c4 Section: embedded Priority: optional Homepage: http://openocd.sourceforge.net/ Description: Open on-chip JTAG/SWD debug solution for embedded target devices OpenOCD aims to provide debugging, in-system programming and boundary-scan testing for embedded target devices. . The debugger uses an IEEE 1149-1 compliant JTAG TAP bus master to access on-chip debug functionality available on ARM based microcontrollers or system-on-chip solutions. For MIPS systems the EJTAG interface is supported. Additionally there is support for eSi-RISC, Intel, OpenRISC, RISC-V and ARC controllers. . User interaction is realized through a telnet command line interface, a gdb (the GNU debugger) remote protocol server, and a simplified RPC connection that can be used to interface with OpenOCD's Jim Tcl engine. . OpenOCD supports many different types of JTAG interfaces/programmers. Package: verilator-4.032 Version: 4.032-1 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 18181 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.032_4.032-1_amd64.deb Size: 3902280 MD5sum: d926647eabb87799c8f44918c235628d SHA1: b181202e2f4d677b8adabb1cefdfe1fa82868eed SHA256: 0150a973954d978a8c4e5f74dd5322adb6e7d760400dfc3717a986fcb15d3bfc Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.034 Version: 4.034-1 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 18664 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.034_4.034-1_amd64.deb Size: 4033344 MD5sum: fda14a05f782ae87a75d181539692456 SHA1: 3269b0bdd59d0d469fe25b7d07c0f33e0b04a638 SHA256: fa47e9b49ee03f3ec3a07c037aba1923477bdc258cb6ef524cd2b3033dfe046b Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.040 Version: 4.040-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 19341 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.040_4.040-0_amd64.deb Size: 4220232 MD5sum: d77a52bbfe58336749ed7801e6eebf84 SHA1: 97781b9673168570b2884f1a8f81511a354fe758 SHA256: 7501186ea6054a1d0bcc7b1dc75172610e1089a9a51a82a57156c95e512f14e9 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.100 Version: 4.100-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 19643 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.100_4.100-0_amd64.deb Size: 4317656 MD5sum: 452e9758fc7bc449b0b8c1060bd40863 SHA1: 7c9ed50d67e9915f427b2429f535b5baa16b256b SHA256: 4061b78ceb606b71e6f4e6fe00fe636eb96d74e911f63a94f82c6046caf904d3 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.102 Version: 4.102-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 19625 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.102_4.102-0_amd64.deb Size: 4293380 MD5sum: 3a770b83c8fc00c40a94fdff5b49e4a3 SHA1: f2946e3e6f75bf8cd76e5cfaaf1be571ae93bfad SHA256: f974015f285b9289f23911a89c1b8ae8008f3c16534e59b1d3fc0d0e4f9a0726 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.104 Version: 4.104-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 19809 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.104_4.104-0_amd64.deb Size: 4345812 MD5sum: 56a31ffe3a12b9def85fa1351da7663a SHA1: d8edc8f2b597ebb674a23221ce7e62e2995417f3 SHA256: 6219839ed4b0e1e8e9e6ca589c23230a56fbb4f3422b57d77592f93bdef66567 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.106 Version: 4.106-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 19938 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.106_4.106-0_amd64.deb Size: 4356368 MD5sum: e0e83afa16a436d706ac58d965d3e790 SHA1: 4182be1b410a725d8ec2cce52fb5413ac1c09938 SHA256: 2f1754d8a66ac4fb16bbc0753d84605121f50581a8d924e61c8f3c3fa2404d47 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.108 Version: 4.108-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 20164 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.108_4.108-0_amd64.deb Size: 4410500 MD5sum: 865f1c20a134b6ea92f404ec5adff7bf SHA1: acc9cdf0859b7f57f801adc4f8799cbca4c169d8 SHA256: c615225b438e7151fb13a621aee64a9622fb34cdb68ac2a0a2cd26e894a78ee8 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.110 Version: 4.110-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 20245 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.110_4.110-0_amd64.deb Size: 4432076 MD5sum: db0034504200d071d3095d3cab6bc811 SHA1: c7d38f25c15a2a5d4e6e9a97ed0e232c5729b29f SHA256: 2656026f75ae1c7ae5d8e1ca381271f4cd27c5c8f602e65cba11613c80f2fc74 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.200 Version: 4.200-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 20279 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.200_4.200-0_amd64.deb Size: 4445164 MD5sum: 1e7f7b15a766eee00e17e620edc0f84d SHA1: b6bd38851b5c711c8bc0e13b1e643e2fa8be195e SHA256: c08622db40c617826101bffc03d21377a015a48b288ee0b7e45dc817af259300 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.202 Version: 4.202-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 20249 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.202_4.202-0_amd64.deb Size: 4369532 MD5sum: aecb654efc723fa7641a3f46d1d45367 SHA1: 128504f21fee013f38e230d8ddb440a8dced80d2 SHA256: 8e6baf96fd15b8663e67c03257c5a05e2282b71ea70022e2f0b6619e166d2dff Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.210 Version: 4.210-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 21741 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.210_4.210-0_amd64.deb Size: 4587036 MD5sum: fb2ba75fc31a08eeaa6bcf1f33999c7a SHA1: 1d54cfbb5e59644dd06633db67c0a88c98fa44a8 SHA256: 022b1dcb10f691af79cbffd359d95661b3cd49f07b5d583dd99a0a00f13e1a68 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams. Package: verilator-4.212 Version: 4.212-0 Architecture: amd64 Maintainer: Philipp Wagner <mail@philipp-wagner.com> Installed-Size: 21969 Depends: libc6 (>= 2.14), perl, perl-doc Filename: ./amd64/verilator-4.212_4.212-0_amd64.deb Size: 4633896 MD5sum: 0c2e3475e59f09dbd4f7023f919b1af5 SHA1: b485ffa1d1231545657e73fd87c7a359eb36a67c SHA256: 4583ce434cfb2b6997268406fc3e6addbe00aa8128c13ed30c13d55e53d61728 Section: electronics Priority: optional Homepage: https://www.verilator.org Description: fast free Verilog simulator Verilator is the fastest free Verilog HDL simulator, and beats many commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.