Package: openocd-0.11.0
Version: 0.11.0-1
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 5232
Depends: libc6 (>= 2.15), libcapstone3 (>= 3.0.0), libftdi1-2 (>= 1.2), libgpiod2 (>= 1.1), libhidapi-hidraw0 (>= 0.8.0~rc1+git20140201.3a66d4e+dfsg), libjim0.79 (>= 0.73), libusb-0.1-4 (>= 2:0.1.12), libusb-1.0-0 (>= 2:1.0.16)
Filename: ./amd64/openocd-0.11.0_0.11.0-1_amd64.deb
Size: 1516208
MD5sum: b012057dfe99522d6740b20acaaa5be6
SHA1: 232a8c5622986cc7f7a3b87a031d2277c780b7df
SHA256: 0914067d43ad9a64a4851f3c453f718011b8251df6b34758e610e89453866027
Section: embedded
Priority: optional
Homepage: http://openocd.sourceforge.net/
Description: Open on-chip JTAG/SWD debug solution for embedded target devices
 OpenOCD aims to provide debugging, in-system programming and boundary-scan
 testing for embedded target devices.
 .
 The debugger uses an IEEE 1149-1 compliant JTAG TAP bus master to access
 on-chip debug functionality available on ARM based microcontrollers or
 system-on-chip solutions. For MIPS systems the EJTAG interface is supported.
 Additionally there is support for eSi-RISC, Intel, OpenRISC, RISC-V and ARC
 controllers.
 .
 User interaction is realized through a telnet command line interface,
 a gdb (the GNU debugger) remote protocol server, and a simplified RPC
 connection that can be used to interface with OpenOCD's Jim Tcl engine.
 .
 OpenOCD supports many different types of JTAG interfaces/programmers.

Package: verilator-4.032
Version: 4.032-1
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 19270
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.032_4.032-1_amd64.deb
Size: 4196032
MD5sum: 09b3a3077f1a9b1c8b75b7d42fb7dcb2
SHA1: b2b45b527b71a1c475c350731655ffa9e784abee
SHA256: a33cb8907b68addae85c8e2521bc415a425a77b691e36f4b7673156075cb480c
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.034
Version: 4.034-1
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 19772
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.034_4.034-1_amd64.deb
Size: 4297288
MD5sum: 62bcf8f033773a803324f4e504b948c1
SHA1: 93890516c59e4effccdc39b2229789a4830d8b55
SHA256: 82af66a43163ec5bb56df067089d78735c62a280448039a7755fe46c06d97e88
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.040
Version: 4.040-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 20742
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.040_4.040-0_amd64.deb
Size: 4513232
MD5sum: b42ed478b1345fe9e8de969f58ed4b9d
SHA1: de0c9c19da0bf3fd5d53a08a74034bc9e2d82065
SHA256: 14dffa024de6352760ec8ae3f2aaf437415d531040cae02606f285eb677e344a
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.100
Version: 4.100-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21100
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.100_4.100-0_amd64.deb
Size: 4650524
MD5sum: 52bc7d6f9331c925ac3f435a23816592
SHA1: eccbea5e7934964e9d042ee6449f491c566ce7df
SHA256: 59c43bb77226e8777faa0796ff09243a73b175aa8f63abf07b1de637a45d2d39
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.102
Version: 4.102-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21062
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.102_4.102-0_amd64.deb
Size: 4627072
MD5sum: 77dad2dc83754b885107bed09e9593ac
SHA1: ae9865a9242617af53e0b1bbd8a25722de0870fd
SHA256: 9763dac192c8dd131727eff0c7c3c946f1b3576fa023ffc0a36412cd222b4f43
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.104
Version: 4.104-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21326
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.104_4.104-0_amd64.deb
Size: 4670184
MD5sum: 26bf929040ae6c99b95187c91c68d53f
SHA1: 43062902baec3e4dbc081b0b289ce98861df53c1
SHA256: 045a30e0a3254372b7729b7c3cd57cb6ef1caced8fd00d9f3a8b77fee9136352
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.106
Version: 4.106-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21439
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.106_4.106-0_amd64.deb
Size: 4683732
MD5sum: 9c00e2c8ca82e1665ca6c73557ee815a
SHA1: 56eeea8264a9cb95071f1923d0d72757cfa5f358
SHA256: 4c9591758f87659f65a0e2a98df0c716282254e76ca3d30fc6e750d31cf04acb
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.108
Version: 4.108-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21689
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.108_4.108-0_amd64.deb
Size: 4732428
MD5sum: bd6cd2c4d3d567bbf2357628563042b9
SHA1: c5db04283f44809745ba37958ec9abe771d2bf67
SHA256: 03af0b9e883044e651b3e64143d44447f01877ccc94b8e8916bda484cce29113
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.110
Version: 4.110-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21778
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.110_4.110-0_amd64.deb
Size: 4778884
MD5sum: 74c88f9d3c438a4eb0cf77a7c8ba688d
SHA1: 5d4e3719ee1ccd3e62d343971a50324be3202aca
SHA256: fb6c8bedae971d1b6b21f9d83cef14d0525d159b4969b48e123495e42157e591
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.200
Version: 4.200-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21820
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.200_4.200-0_amd64.deb
Size: 4804204
MD5sum: a219c94a405e5e69e6fbe8292eb64003
SHA1: 10f8fe9ed4adeec8757e3cf2e3b3df2e4ec36e51
SHA256: 650fe73698d87ab769269d067a2e2905b547044dcda8cddff84d24af67e1ec1d
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.202
Version: 4.202-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 21810
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.202_4.202-0_amd64.deb
Size: 4739768
MD5sum: 9b078872cbdd3d3734798a102cbdba85
SHA1: ebcf8c81cb251b3cdc98d847747bbce2097a6ca4
SHA256: 39058ebb91d9f6f0301503c6a97bd9a34c1c91dd6fea7b97b42f91c202757efa
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.210
Version: 4.210-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 23634
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.210_4.210-0_amd64.deb
Size: 4832476
MD5sum: f0739362fede334bf7297a38e7ecbc2f
SHA1: e7220b109f8c3a785eccd8cb82582ca348953288
SHA256: 2070190a89899de518b79a3d2120e85c415677733d1a49a805b80c25737519f6
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.

Package: verilator-4.212
Version: 4.212-0
Architecture: amd64
Maintainer: Philipp Wagner <mail@philipp-wagner.com>
Installed-Size: 23874
Depends: libc6 (>= 2.29), perl, perl-doc
Filename: ./amd64/verilator-4.212_4.212-0_amd64.deb
Size: 4907140
MD5sum: 10fca9fc62cc4c5a70e748da63ca606f
SHA1: 4e4f1547d545ffe062c1fefaf21dc2579a355ddb
SHA256: 7270edb8f161e095e6c81fc475bca6f5ed2635265125e1a15e0c042316ae10bc
Section: electronics
Priority: optional
Homepage: https://www.verilator.org
Description: fast free Verilog simulator
 Verilator is the fastest free Verilog HDL simulator, and beats many commercial
 simulators. It compiles synthesizable Verilog (not test-bench code!), plus
 some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code.
 It is designed for large projects where fast simulation performance is of
 primary concern, and is especially well suited to generate executable models
 of CPUs for embedded software design teams.