Package: cocotb Version: 1.5.2-c4m.1+6.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1946 Depends: libc6 (>= 2.14), libgcc-s1 (>= 3.3.1), libstdc++6 (>= 5.2), python Filename: ./amd64/cocotb_1.5.2-c4m.1+6.1_amd64.deb Size: 286064 MD5sum: 7ee7e8397be7b8e0b64c9827ef884aea SHA1: 231501a52785ef564454deafc3e5e4997b62eebb SHA256: 4a64cffd3e85a0a0f45f7e596359811f177d3467611e217eb098fef9b24a88d6 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: ghdl Version: 1.0.1.dev20210706.git1285cbf-c4m.1+4.1 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 20257 Depends: libc6 (>= 2.29), libgcc-s1 (>= 3.0), libgnat-10 (>= 10), zlib1g (>= 1:1.2.0) Filename: ./amd64/ghdl_1.0.1.dev20210706.git1285cbf-c4m.1+4.1_amd64.deb Size: 3031484 MD5sum: fa69d258f94b2283b89a9b2325ab2540 SHA1: 59f277c77a6b2324ba352a917cf3cea18a2849e1 SHA256: 819cd1daaacc30902527f4c6d2e6b6dedfabbb2b72b1f27775cafb577aaa5bfb Section: electronics Priority: extra Description: GHDL GHDL is the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language. GHDL is not an interpreter: it allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation. Package: ghdl-yosys-plugin Version: 0.0.0.dev20210327.git5fad8b9-c4m.1+3.3 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 145 Depends: ghdl, yosys Filename: ./amd64/ghdl-yosys-plugin_0.0.0.dev20210327.git5fad8b9-c4m.1+3.3_amd64.deb Size: 38500 MD5sum: 604c42be7ecb7b0fbdb6c0a7632f214f SHA1: f1e6287d1d607b8cd214c1ab2742bdc7b9dc66a2 SHA256: 2bb509ecc3d5c74f47c559beadb54b1dc234db5ce29b7e7b269a4e7da48f12b5 Section: electronics Priority: extra Description: VHDL synthesis VHDL synthesis (based on GHDL and Yosys) Package: gtkwave Version: 3.3.110-c4m.1+3.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 4588 Depends: libbz2-1.0, libc6 (>= 2.29), libcairo2 (>= 1.10.0), libgcc-s1 (>= 3.0), libgdk-pixbuf2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.49.3), libgtk-3-0 (>= 3.21.5), libjudydebian1, liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/gtkwave_3.3.110-c4m.1+3.1_amd64.deb Size: 2381824 MD5sum: 850a813732417cc76522791ee05d3d25 SHA1: 42b2741fc1aa3b432195b1c313273a86ec05e8e5 SHA256: 7e755081c91830e2f6d9f77f76b665c1804d59dfa7328587c19e13ab9f7fd37a Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing. Package: iverilog Version: 11.0-c4m.1+4.1 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 6694 Depends: libc6 (>= 2.29), libgcc-s1 (>= 3.0), libreadline8 (>= 6.0), libstdc++6 (>= 5.2), zlib1g (>= 1:1.2.0) Filename: ./amd64/iverilog_11.0-c4m.1+4.1_amd64.deb Size: 1929548 MD5sum: 78d81b38e2d04e822416fc37088442a2 SHA1: 10c745b927c66c8682f52ddba0874b03813ca474 SHA256: 5f796b124079d01180cd8fd3b672d14a056ec61223d8d7b613867804a4af64e0 Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. Package: klayout Version: 0.27.2-c4m.1+5.1 Architecture: amd64 Maintainer: Matthias Köfferlein Installed-Size: 194224 Depends: libc6 (>= 2.29), libgcc-s1 (>= 3.0), libpython3.8 (>= 3.8.2), libqt5core5a (>= 5.12.2), libqt5designer5 (>= 5.6.0~beta), libqt5gui5 (>= 5.9.0~beta3) | libqt5gui5-gles (>= 5.9.0~beta3), libqt5multimedia5 (>= 5.6.0~beta), libqt5multimediawidgets5 (>= 5.6.0~beta), libqt5network5 (>= 5.5.0), libqt5printsupport5 (>= 5.4.0), libqt5sql5 (>= 5.10.0), libqt5svg5 (>= 5.6.0~beta), libqt5widgets5 (>= 5.12.2), libqt5xml5 (>= 5.1.0), libqt5xmlpatterns5 (>= 5.9.0), libruby2.7 (>= 2.7.0), libstdc++6 (>= 5.2), zlib1g (>= 1:1.1.4) Filename: ./amd64/klayout_0.27.2-c4m.1+5.1_amd64.deb Size: 35527940 MD5sum: b7ae36f1d0a4996b56e03de1fb469b83 SHA1: 64dfa11ad1f2eb323159c72cd0e9bb168cddc174 SHA256: 5036f64182f295b190761c7ed5dc3396092308ff3fb3623e916125f67cf1e4ae Section: electronics Priority: optional Description: Chip mask layout review and edit utility Klayout is a graphical viewer and editor for a.o. GDSII, OASIS, CIF and other files. Its features include net highlighting and XOR-ing of two layouts, scripting capabilities in Ruby and Python and much more. Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 753 Depends: libc6 (>= 2.29), libtcl8.6 (>= 8.6.0) Filename: ./amd64/netgen-lvs_1.5.133-c4m.0.0_amd64.deb Size: 191128 MD5sum: adce1019d5f097e310c9480de8ca52a1 SHA1: 9bc243a13ca8350c796ca4a034d66b4651db5923 SHA256: ce6cd548d7da3be112cf1d7a81f84a013a68249b0e16a4c0ba1546637c0f16ac Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: opensta Version: 2.2.1.dev20210719.git37cd1fc-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 12192 Depends: libc6 (>= 2.29), libgcc-s1 (>= 3.0), libstdc++6 (>= 6), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/opensta_2.2.1.dev20210719.git37cd1fc-c4m.0.0_amd64.deb Size: 1614476 MD5sum: 67cdf6ff89bc1e065d48f8621d9fde2a SHA1: 661d7fa059d14468a6e17274ba383399716af67c SHA256: bb630931ed21da91f4172470e0c190f93db788f42b71850a52b9ec2107f5ee0e Section: electronics Priority: extra Description: OpenSTA is a gate level static timing verifier Package: opentimer Version: 0.0.0.dev20210719.git8fb20ff-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 19987 Depends: libc6 (>= 2.14), libgcc-s1 (>= 3.0), libstdc++6 (>= 9) Filename: ./amd64/opentimer_0.0.0.dev20210719.git8fb20ff-c4m.0.0_amd64.deb Size: 1558112 MD5sum: e155dcd42386b4559528383b32374fa1 SHA1: b2ba2995858f40d598f2bf7813b0106bae59d1c4 SHA256: 8324b7c4da1722d6ddac8d18be93c3c863b3a674db7ba14b88ed5e799c6fc1c3 Section: electronics Priority: extra Description: A High-Performance Timing Analysis Tool for VLSI Systems Package: verilator Version: 4.106-c4m.1+6.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 21439 Depends: zlib1g-dev, libc6 (>= 2.29) Filename: ./amd64/verilator_4.106-c4m.1+6.1_amd64.deb Size: 4678904 MD5sum: 3af7de09a40040cf266ec85944fb3c0f SHA1: 5455157435716390ba3c3194223f7c48ff165d69 SHA256: 7cdfe097e13a7097bbd27973b1a526049a1ed9caf990605aa0fe328c4877a606 Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: yosys Version: 0.9+4081-c4m.1+6.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 38696 Depends: libc6 (>= 2.29), libffi7 (>= 3.3~20180313), libgcc-s1 (>= 3.0), libreadline8 (>= 6.0), libstdc++6 (>= 9), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/yosys_0.9+4081-c4m.1+6.1_amd64.deb Size: 10938052 MD5sum: 56dedd801cf0402c277470f3efb09bb8 SHA1: b1a8f60ecbcba0c57e42582eb8e574bb50ed901d SHA256: 761d29f498c50ad66ea425172b086bc783d7473407ccd7231b4f0ff77ba46a1c Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/