i[8ch(c0(,chipspark,rayeager-px2rockchip,rk3066a 7Rayeager PX2aliases=/ethernet@10204000G/i2c@2002d000L/i2c@2002f000Q/i2c@20056000V/i2c@2005a000[/i2c@2005e000`/mmc@1021c000f/mmc@10214000l/mmc@10218000r/serial@10124000z/serial@10126000/serial@20064000/serial@20068000/spi@20070000/spi@20074000bus ,simple-busdma-controller@20018000,arm,pl330arm,primecell @ apb_pclkdma-controller@2001c000,arm,pl330arm,primecell @ apb_pclk  disableddma-controller@20078000,arm,pl330arm,primecell @ apb_pclkoscillator ,fixed-clockn6!.xin24mgpu@10090000",rockchip,rk3066-maliarm,mali-400  buscoreAQfx  disabledx5mgpgpmmupp0ppmmu0pp1ppmmu1pp2ppmmu2pp3ppmmu3}cache-controller@10138000,arm,pl310-cacheHscu@1013c000,arm,cortex-a9-scuglobal-timer@1013c200,arm,cortex-a9-global-timer     disabledlocal-timer@1013c600,arm,cortex-a9-twd-timer   interrupt-controller@1013d000,arm,cortex-a9-gicserial@10124000&,rockchip,rk3066-uartsnps,dw-apb-uart@ "baudclkapb_pclk@L okaytxrxdefault serial@10126000&,rockchip,rk3066-uartsnps,dw-apb-uart` #baudclkapb_pclkAM  disabledtxrxdefaultqos@1012d000,syscon )qos@1012e000,syscon (qos@1012f000,syscon "qos@1012f080,syscon $qos@1012f100,syscon &qos@1012f180,syscon #qos@1012f200,syscon %qos@1012f280,syscon 'usb@10180000,rockchip,rk3066-usbsnps,dwc2 otg otg#2@@ A  Fusb2-phy okayusb@101c0000 ,snps,dwc2 otg hostA  Fusb2-phy okaydefault ethernet@10204000,rockchip,rk3066-emac @< P D hclkmacref]dgrmii okaydefault ptethernet-phy@0 mmc@10214000,rockchip,rk2928-dw-mshc!@ Hbiuciurx-txfQreset okaydefaultmmc@10218000,rockchip,rk2928-dw-mshc! Ibiuciurx-txfRreset okaydefault mmc@1021c000,rockchip,rk2928-dw-mshc! Jbiuciurx-txfSreset okaydefault  !!pmu@20004000&,rockchip,rk3066-pmusysconsimple-mfd @reboot-mode,syscon-reboot-mode@RB"RB0RB @RBpower-controller!,rockchip,rk3066-power-controllerLpower-domain@7PO`"#$%&'power-domain@6 `(power-domain@8`)grf@20008000,syscon  i2c@2002d000,rockchip,rk3066-i2c  (P i2cP okaydefault*ak8963@d,asahi-kasei,ak8975 +default,mma8452@1d ,fsl,mma8452+default-i2c@2002f000,rockchip,rk3066-i2c  )P Qi2c okaydefault.tps@2d-/default01g2s2223322 ,ti,tps65910regulatorsregulator@0vcc_rtcvrtcregulator@1vcc_io2Z2Zvio3regulator@2vdd_arm '`0vdd1Iregulator@3vcc_ddr '`0vdd2regulator@5vcc18w@w@vdig1regulator@6vdd_11vdig2regulator@7vcc_25&%&%vpll?regulator@8 vccio_wlw@w@vdacregulator@9 vcc25_hdmi&%&% vaux1regulator@10vcca_332Z2Z vaux2regulator@11 vcc_rmii2Z2Z vaux33regulator@12 vcc28_cif** vmmcregulator@4vdd3regulator@13 vbbpwm@20030000,rockchip,rk2928-pwm BF  disableddefault4pwm@20030010,rockchip,rk2928-pwm BF okaydefault5watchdog@2004c000 ,rockchip,rk3066-wdtsnps,dw-wdt K 3 okaypwm@20050020,rockchip,rk2928-pwm  BG okaydefault6pwm@20050030,rockchip,rk2928-pwm 0BG okaydefault7Zi2c@20056000,rockchip,rk3066-i2c ` *P Ri2c okaydefault8i2c@2005a000,rockchip,rk3066-i2c  +P Si2c okaydefault9i2c@2005e000,rockchip,rk3066-i2c  4P Ti2c okaydefault:serial@20064000&,rockchip,rk3066-uartsnps,dw-apb-uart @ $baudclkapb_pclkBN okaytxrxdefault;serial@20068000&,rockchip,rk3066-uartsnps,dw-apb-uart  %baudclkapb_pclkCO okay txrxdefault <=>saradc@2006c000,rockchip,saradc  MGJsaradcapb_pclkfW saradc-apb okay_?spi@20070000,rockchip,rk3066-spiEHspiclkapb_pclk &   txrx okaydefault@ABCspi@20074000,rockchip,rk3066-spiFIspiclkapb_pclk ' @  txrx  disableddefaultDEFGcpuskrockchip,rk3066-smpcpu@0ycpu,arm,cortex-a9H8@ Oa* s* 'g8@Icpu@1ycpu,arm,cortex-a9HIdisplay-subsystem,rockchip,display-subsystemJKsram@10080000 ,mmio-sram smp-sram@0,rockchip,rk3066-smp-sramPvop@1010c000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop}fdef axiahbdclk  disabledportJendpoint@0LPvop@1010e000,rockchip,rk3066-vop aclk_vopdclk_vophclk_vop}fghi axiahbdclk  disabledportKendpoint@0MQhdmi@10116000,rockchip,rk3066-hdmi`  @hclkdefaultNO}P   disabledportsport@0endpoint@0PLendpoint@1QMport@1i2s@10118000,rockchip,rk3066-i2s  defaultRKi2s_clki2s_hclktxrx   disabledi2s@1011a000,rockchip,rk3066-i2s  defaultSLi2s_clki2s_hclktxrx   disabledi2s@1011c000,rockchip,rk3066-i2s  defaultTMi2s_clki2s_hclk  txrx   disabledclock-controller@20000000,rockchip,rk3066a-cru P !@A^_ Qׄ#gрxhрxhtimer@2000e000,snps,dw-apb-timer-osc  .VD timerpclkefuse@20010000,rockchip,rk3066a-efuse @[ pclk_efusecpu_leakage@17timer@20038000,snps,dw-apb-timer-osc  ,TB timerpclktimer@2003a000,snps,dw-apb-timer-osc  -UC timerpclktsadc@20060000,rockchip,rk3066-tsadc ]]saradcapb_pclk Mf\ saradc-apb  disabledphy1,rockchip,rk3066a-usb-phyrockchip,rk3288-usb-phyP  okayusb-phy@17c)|Qphyclk! usb-phy@188)Rphyclk! pinctrl,rockchip,rk3066a-pinctrlP gpio0@20034000,rockchip,gpio-bank @ 6U4D_gpio1@2003c000,rockchip,gpio-bank  7V4Dgpio2@2003e000,rockchip,gpio-bank  8W4Dgpio3@20080000,rockchip,gpio-bank  9X4D]gpio4@20084000,rockchip,gpio-bank @ :Y4D+gpio6@2000a000,rockchip,gpio-bank  <Z4D/pcfg_pull_defaultPWpcfg_pull_nonefUemacemac-xfersUUUUUUUUemac-mdio sUUrmii-rstsVemmcemmc-clksWemmc-cmds Wemmc-rsts W hdmihdmi-hpdsWOhdmii2c-xfer sUUNi2c0i2c0-xfer sUU*i2c1i2c1-xfer sUU.i2c2i2c2-xfer sUU8i2c3i2c3-xfer sUU9i2c4i2c4-xfer sUU:pwm0pwm0-outsU4pwm1pwm1-outsU5pwm2pwm2-outsU6pwm3pwm3-outsU7spi0spi0-clksW@spi0-cs0sWCspi0-txsWAspi0-rxsWBspi0-cs1sWspi1spi1-clksWDspi1-cs0sWGspi1-rxsWFspi1-txsWEspi1-cs1sWuart0uart0-xfer sWWuart0-ctssWuart0-rtssWuart1uart1-xfer sWWuart1-ctssWuart1-rtssWuart2uart2-xfer sW W;uart3uart3-xfer sWW<uart3-ctssW=uart3-rtssW>sd0sd0-clksWsd0-cmds Wsd0-cdsWsd0-wpsWsd0-bus-width1s Wsd0-bus-width4@s W W W Wsd1sd1-clksWsd1-cmdsWsd1-cdsWsd1-wpsWsd1-bus-width1sWsd1-bus-width4@sWWWWi2s0i2s0-bussWW W W W W WWWRi2s1i2s1-bus`sWWWWWWSi2s2i2s2-bus`sWWWWWWTpcfg-output-highVak8963comp-intsW,irir-intsWXkeyspwr-keysWYmma8452gsensor-intsW-mmcsdmmc-pwrsW^usb_hosthost-drvsW`hub-rstsV sata-pwrsW[sata-resets V usb_otgotg-drvsWatpspmic-intsW0pwr-holdsV1memory@60000000ymemory`@ir-receiver,gpio-ir-receiver /defaultXgpio-keys ,gpio-keyspower / GPIO PowertdefaultYvdd-log,pwm-regulator Zvdd_logOOB@dO* okayvsys-regulator,regulator-fixedvsysLK@LK@025v-stdby-regulator,regulator-fixed 5v_stdbyLK@LK@0\emmc-regulator,regulator-fixed emmc_vccq--2!sata-regulator,regulator-fixed +default[usb_5vLK@LK@\sdmmc-regulator,regulator-fixed ]default^vcc_sd2Z2Z3usb-host-regulator,regulator-fixed _default` host-pwrLK@LK@\usb-otg-regulator,regulator-fixed _defaultavcc_otgLK@LK@\ #address-cells#size-cellsinterrupt-parentcompatiblemodelethernet0i2c0i2c1i2c2i2c3i2c4mshc0mshc1mshc2serial0serial1serial2serial3spi0spi1rangesreginterrupts#dma-cellsarm,pl330-broken-no-flushparm,pl330-periph-burstclocksclock-namesphandlestatusclock-frequency#clock-cellsclock-output-namesassigned-clocksassigned-clock-ratesresetsinterrupt-namespower-domainscache-unifiedcache-levelinterrupt-controller#interrupt-cellsreg-shiftreg-io-widthdmasdma-namespinctrl-namespinctrl-0dr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephysphy-namesrockchip,grfmax-speedphy-modephyphy-supplyreset-gpiosfifo-depthreset-namesmax-frequencybus-widthdisable-wpvmmc-supplycap-mmc-highspeedcap-sd-highspeednon-removablevqmmc-supplyoffsetmode-normalmode-recoverymode-bootloadermode-loader#power-domain-cellspm_qosvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvccio-supplyregulator-nameregulator-always-onregulator-compatibleregulator-min-microvoltregulator-max-microvoltregulator-boot-on#pwm-cells#io-channel-cellsvref-supplyenable-methoddevice_typenext-level-cacheoperating-pointsclock-latencycpu-supplyportsremote-endpointrockchip,playback-channelsrockchip,capture-channels#sound-dai-cells#reset-cells#phy-cellsgpio-controller#gpio-cellsbias-pull-pin-defaultbias-disablerockchip,pinsoutput-highwakeup-sourcelabellinux,codepwmsvoltage-tablevin-supplyenable-active-highgpiostartup-delay-us