68 (  pUheadacoustics,omap3-ha-lcdtechnexion,omap3-tao3530ti,omap3430ti,omap34xxti,omap3 +77TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOMchosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/displaycpus+cpu@0arm,cortex-a8|cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+ 5Spdefault ~ hsusbb2-pins`          mmc1-pinsP "$&mmc2-pins0(*,.02wlan-gpio-pins^uart3-pinsnApi2c3-pinsmcspi1-pins mcspi3-pins mcbsp3-pins <>@Btwl4030-pinsAsound2-pinsnled-blue-pins led-green-pins led-red-pins poweroff-pinspowerdown-input-pinsfpga-boot0-pins fpga-boot1-pins rtvxtouchscreen-irq-pins4touchscreen-wake-pins dss-dpi-pins lte430-pins8backlight-pins:scm_conf@270sysconsimple-busp0+ p0 pbias_regulator@2b0ti,pbias-omap3ti,pbias-omap pbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselh+clock-mcbsp5-mux-fck@4ti,composite-mux-clockmcbsp5_mux_fckclock-mcbsp3-mux-fck@0ti,composite-mux-clockmcbsp3_mux_fckclock-mcbsp4-mux-fck@2ti,composite-mux-clockmcbsp4_mux_fckmcbsp5_fckti,composite-clockclock@4 ti,clksel+clock-mcbsp1-mux-fck@2ti,composite-mux-clockmcbsp1_mux_fckclock-mcbsp2-mux-fck@6ti,composite-mux-clockmcbsp2_mux_fckmcbsp1_fckti,composite-clockmcbsp2_fckti,composite-clockmcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ 5Stwl4030-vpins-pins target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss  'ick+ H `  4disabledaes1@0 ti,omap3-aesP;  @txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss  'ick+ H P  4disabledaes2@0 ti,omap3-aesP;AB@txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockJY#osc_sys_ck@d40 ti,mux-clock !"# @$sys_ck@1270ti,divider-clock$Zgpr)sys_clkout1@d70ti,gate-clock$ pZdpll3_x2_ckfixed-factor-clock%dpll3_m2x2_ckfixed-factor-clock&(dpll4_x2_ckfixed-factor-clock'corex2_fckfixed-factor-clock(*wkup_l4_ickfixed-factor-clock)icorex2_d3_fckfixed-factor-clock*corex2_d5_fckfixed-factor-clock*clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockJomap_32k_fck fixed-clockJOvirt_12m_ck fixed-clockJvirt_13m_ck fixed-clockJ]@virt_19200000_ck fixed-clockJ$ virt_26000000_ck fixed-clockJ!virt_38_4m_ck fixed-clockJI"dpll4_ck@d00ti,omap3-dpll-per-clock)) D 0'dpll4_m2_ck@d48ti,divider-clock'g? Hr+dpll4_m2x2_mul_ckfixed-factor-clock+,dpll4_m2x2_ck@d00ti,gate-clock,Z -omap_96m_alwon_fckfixed-factor-clock-9dpll3_ck@d00ti,omap3-dpll-core-clock)) @ 0%clock@1140 ti,clksel@+clock-dpll3-m3@16ti,divider-clock dpll3_m3_ck%gr3clock-dpll4-m6@24ti,divider-clock dpll4_m6_ck'g?rEclock-emu-src-mux@0 ti,mux-clockemu_src_mux_ck)./0}clock-pclk-fck@8ti,divider-clock pclk_fck1grclock-pclkx2-fck@6ti,divider-clock pclkx2_fck1grclock-atclk-fck@4ti,divider-clock atclk_fck1grclock-traceclk-src-fck@2 ti,mux-clocktraceclk_src_fck)./02clock-traceclk-fck@11 ti,divider-clock traceclk_fck2grdpll3_m3x2_mul_ckfixed-factor-clock34dpll3_m3x2_ck@d00ti,gate-clock4Z  5emu_core_alwon_ckfixed-factor-clock5.sys_altclk fixed-clockJ<mcbsp_clks fixed-clockJcore_ckfixed-factor-clock&6dpll1_fck@940ti,divider-clock6Zg @r7dpll1_ck@904ti,omap3-dpll-clock)7  $ @ 4dpll1_x2_ckfixed-factor-clock8dpll1_x2m2_ck@944ti,divider-clock8g DrLcm_96m_fckfixed-factor-clock9:clock@d40 ti,clksel @+clock-dpll3-m2@27ti,divider-clock dpll3_m2_ck%gr&clock-omap-96m-fck@6 ti,mux-clock omap_96m_fck:)`clock-omap-54m-fck@5 ti,mux-clock omap_54m_fck;<Hclock-omap-48m-fck@3 ti,mux-clock omap_48m_fck=<@clock@e40 ti,clksel@+clock-dpll4-m3@8ti,divider-clock dpll4_m3_ck'g r>clock-dpll4-m4@0ti,divider-clock dpll4_m4_ck'grAdpll4_m3x2_mul_ckfixed-factor-clock>?dpll4_m3x2_ck@d00ti,gate-clock?Z ;cm_96m_d2_fckfixed-factor-clock:=omap_12m_fckfixed-factor-clock@adpll4_m4x2_mul_ckti,fixed-factor-clockABdpll4_m4x2_ck@d00ti,gate-clockBZ edpll4_m5_ck@f40ti,divider-clock'g?@rCdpll4_m5x2_mul_ckti,fixed-factor-clockCDdpll4_m5x2_ck@d00ti,gate-clockDZ dpll4_m6x2_mul_ckfixed-factor-clockEFdpll4_m6x2_ck@d00ti,gate-clockFZ Gemu_per_alwon_ckfixed-factor-clockG/clock@d70 ti,clksel p+clock-clkout2-src-gate@7 ti,composite-no-wait-gate-clockclkout2_src_gate_ck6Jclock-clkout2-src-mux@0ti,composite-mux-clockclkout2_src_mux_ck6):HKclock-sys-clkout2@3ti,divider-clock sys_clkout2Ig@clkout2_src_ckti,composite-clockJKImpu_ckfixed-factor-clockLMarm_fck@924ti,divider-clockM $gemu_mpu_alwon_ckfixed-factor-clockM0clock@a40 ti,clksel @+clock-l3-ick@0ti,divider-clockl3_ick6grNclock-l4-ick@2ti,divider-clockl4_ickNgrPclock-gpt10-mux-fck@6ti,composite-mux-clockgpt10_mux_fckO)]clock-gpt11-mux-fck@7ti,composite-mux-clockgpt11_mux_fckO)_clock-ssi-ssr-div-fck-3430es2@8ti,composite-divider-clockssi_ssr_div_fck_3430es2*$clock@c40 ti,clksel @+clock-rm-ick@1ti,divider-clockrm_ickPgrclock-gpt1-mux-fck@0ti,composite-mux-clock gpt1_mux_fckO)hclock-usim-mux-fck@3ti,composite-mux-clock usim_mux_fck()QRSTUVWXYrclock@a00 ti,clksel +clock-gpt10-gate-fck@11 ti,composite-gate-clockgpt10_gate_fck)\clock-gpt11-gate-fck@12 ti,composite-gate-clockgpt11_gate_fck)^clock-mmchs2-fck@25ti,wait-gate-clock mmchs2_fckclock-mmchs1-fck@24ti,wait-gate-clock mmchs1_fckclock-i2c3-fck@17ti,wait-gate-clock i2c3_fckclock-i2c2-fck@16ti,wait-gate-clock i2c2_fckclock-i2c1-fck@15ti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fck@10 ti,composite-gate-clockmcbsp5_gate_fckclock-mcbsp1-gate-fck@9 ti,composite-gate-clockmcbsp1_gate_fckclock-mcspi4-fck@21ti,wait-gate-clock mcspi4_fckZclock-mcspi3-fck@20ti,wait-gate-clock mcspi3_fckZclock-mcspi2-fck@19ti,wait-gate-clock mcspi2_fckZclock-mcspi1-fck@18ti,wait-gate-clock mcspi1_fckZclock-uart2-fck@14ti,wait-gate-clock uart2_fckZclock-uart1-fck@13 ti,wait-gate-clock uart1_fckZclock-hdq-fck@22ti,wait-gate-clockhdq_fck[clock-modem-fck@31ti,omap3-interface-clock modem_fck)clock-mspro-fck@23ti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2@0 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2*clock-mmchs3-fck@30ti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clock\]gpt11_fckti,composite-clock^_core_96m_fckfixed-factor-clock`core_48m_fckfixed-factor-clock@Zcore_12m_fckfixed-factor-clocka[core_l3_ickfixed-factor-clockNbclock@a10 ti,clksel +clock-sdrc-ick@1ti,wait-gate-clock sdrc_ickbclock-mmchs2-ick@25ti,omap3-interface-clock mmchs2_ickcclock-mmchs1-ick@24ti,omap3-interface-clock mmchs1_ickcclock-hdq-ick@22ti,omap3-interface-clockhdq_ickcclock-mcspi4-ick@21ti,omap3-interface-clock mcspi4_ickcclock-mcspi3-ick@20ti,omap3-interface-clock mcspi3_ickcclock-mcspi2-ick@19ti,omap3-interface-clock mcspi2_ickcclock-mcspi1-ick@18ti,omap3-interface-clock mcspi1_ickcclock-i2c3-ick@17ti,omap3-interface-clock i2c3_ickcclock-i2c2-ick@16ti,omap3-interface-clock i2c2_ickcclock-i2c1-ick@15ti,omap3-interface-clock i2c1_ickcclock-uart2-ick@14ti,omap3-interface-clock uart2_ickcclock-uart1-ick@13 ti,omap3-interface-clock uart1_ickcclock-gpt11-ick@12 ti,omap3-interface-clock gpt11_ickcclock-gpt10-ick@11 ti,omap3-interface-clock gpt10_ickcclock-mcbsp5-ick@10 ti,omap3-interface-clock mcbsp5_ickcclock-mcbsp1-ick@9 ti,omap3-interface-clock mcbsp1_ickcclock-omapctrl-ick@6ti,omap3-interface-clock omapctrl_ickcclock-aes2-ick@28ti,omap3-interface-clock aes2_ickcclock-sha12-ick@27ti,omap3-interface-clock sha12_ickcclock-icr-ick@29ti,omap3-interface-clockicr_ickcclock-des2-ick@26ti,omap3-interface-clock des2_ickcclock-mspro-ick@23ti,omap3-interface-clock mspro_ickcclock-mailboxes-ick@7ti,omap3-interface-clockmailboxes_ickcclock-sad2d-ick@3ti,omap3-interface-clock sad2d_ickNclock-hsotgusb-ick-3430es2@4"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2bclock-ssi-ick-3430es2@0ti,omap3-ssi-interface-clockssi_ick_3430es2dclock-mmchs3-ick@30ti,omap3-interface-clock mmchs3_ickcgpmc_fckfixed-factor-clockbcore_l4_ickfixed-factor-clockPcclock@e00 ti,clksel+clock-dss-tv-fckti,gate-clock dss_tv_fckHZclock-dss-96m-fckti,gate-clock dss_96m_fck`Zclock-dss2-alwon-fckti,gate-clockdss2_alwon_fck)Zclock-dss1-alwon-fck-3430es2@0ti,dss-gate-clockdss1_alwon_fck_3430es2edummy_ck fixed-clockJclock@c00 ti,clksel +clock-gpt1-gate-fck@0ti,composite-gate-clockgpt1_gate_fck)gclock-gpio1-dbck@3ti,gate-clock gpio1_dbckfclock-wdt2-fck@5ti,wait-gate-clock wdt2_fckfclock-sr1-fck@6ti,wait-gate-clocksr1_fck)clock-sr2-fck@7ti,wait-gate-clocksr2_fck)clock-usim-gate-fck@9 ti,composite-gate-clockusim_gate_fck`gpt1_fckti,composite-clockghwkup_32k_fckfixed-factor-clockOfclock@c10 ti,clksel +clock-wdt2-ick@5ti,omap3-interface-clock wdt2_ickiclock-wdt1-ick@4ti,omap3-interface-clock wdt1_ickiclock-gpio1-ick@3ti,omap3-interface-clock gpio1_ickiclock-omap-32ksync-ick@2ti,omap3-interface-clockomap_32ksync_ickiclock-gpt12-ick@1ti,omap3-interface-clock gpt12_ickiclock-gpt1-ick@0ti,omap3-interface-clock gpt1_ickiclock-usim-ick@9 ti,omap3-interface-clock usim_ickiper_96m_fckfixed-factor-clock9per_48m_fckfixed-factor-clock@jclock@1000 ti,clksel+clock-uart3-fck@11 ti,wait-gate-clock uart3_fckjclock-gpt2-gate-fck@3ti,composite-gate-clockgpt2_gate_fck)lclock-gpt3-gate-fck@4ti,composite-gate-clockgpt3_gate_fck)nclock-gpt4-gate-fck@5ti,composite-gate-clockgpt4_gate_fck)pclock-gpt5-gate-fck@6ti,composite-gate-clockgpt5_gate_fck)rclock-gpt6-gate-fck@7ti,composite-gate-clockgpt6_gate_fck)tclock-gpt7-gate-fck@8ti,composite-gate-clockgpt7_gate_fck)vclock-gpt8-gate-fck@9 ti,composite-gate-clockgpt8_gate_fck)xclock-gpt9-gate-fck@10 ti,composite-gate-clockgpt9_gate_fck)zclock-gpio6-dbck@17ti,gate-clock gpio6_dbckkclock-gpio5-dbck@16ti,gate-clock gpio5_dbckkclock-gpio4-dbck@15ti,gate-clock gpio4_dbckkclock-gpio3-dbck@14ti,gate-clock gpio3_dbckkclock-gpio2-dbck@13 ti,gate-clock gpio2_dbckkclock-wdt3-fck@12 ti,wait-gate-clock wdt3_fckkclock-mcbsp2-gate-fck@0ti,composite-gate-clockmcbsp2_gate_fckclock-mcbsp3-gate-fck@1ti,composite-gate-clockmcbsp3_gate_fckclock-mcbsp4-gate-fck@2ti,composite-gate-clockmcbsp4_gate_fckclock@1040 ti,clksel@+clock-gpt2-mux-fck@0ti,composite-mux-clock gpt2_mux_fckO)mclock-gpt3-mux-fck@1ti,composite-mux-clock gpt3_mux_fckO)oclock-gpt4-mux-fck@2ti,composite-mux-clock gpt4_mux_fckO)qclock-gpt5-mux-fck@3ti,composite-mux-clock gpt5_mux_fckO)sclock-gpt6-mux-fck@4ti,composite-mux-clock gpt6_mux_fckO)uclock-gpt7-mux-fck@5ti,composite-mux-clock gpt7_mux_fckO)wclock-gpt8-mux-fck@6ti,composite-mux-clock gpt8_mux_fckO)yclock-gpt9-mux-fck@7ti,composite-mux-clock gpt9_mux_fckO){gpt2_fckti,composite-clocklmgpt3_fckti,composite-clocknogpt4_fckti,composite-clockpqgpt5_fckti,composite-clockrsgpt6_fckti,composite-clocktugpt7_fckti,composite-clockvwgpt8_fckti,composite-clockxygpt9_fckti,composite-clockz{per_32k_alwon_fckfixed-factor-clockOkper_l4_ickfixed-factor-clockP|clock@1010 ti,clksel+clock-gpio6-ick@17ti,omap3-interface-clock gpio6_ick|clock-gpio5-ick@16ti,omap3-interface-clock gpio5_ick|clock-gpio4-ick@15ti,omap3-interface-clock gpio4_ick|clock-gpio3-ick@14ti,omap3-interface-clock gpio3_ick|clock-gpio2-ick@13 ti,omap3-interface-clock gpio2_ick|clock-wdt3-ick@12 ti,omap3-interface-clock wdt3_ick|clock-uart3-ick@11 ti,omap3-interface-clock uart3_ick|clock-uart4-ick@18ti,omap3-interface-clock uart4_ick|clock-gpt9-ick@10 ti,omap3-interface-clock gpt9_ick|clock-gpt8-ick@9 ti,omap3-interface-clock gpt8_ick|clock-gpt7-ick@8ti,omap3-interface-clock gpt7_ick|clock-gpt6-ick@7ti,omap3-interface-clock gpt6_ick|clock-gpt5-ick@6ti,omap3-interface-clock gpt5_ick|clock-gpt4-ick@5ti,omap3-interface-clock gpt4_ick|clock-gpt3-ick@4ti,omap3-interface-clock gpt3_ick|clock-gpt2-ick@3ti,omap3-interface-clock gpt2_ick|clock-mcbsp2-ick@0ti,omap3-interface-clock mcbsp2_ick|clock-mcbsp3-ick@1ti,omap3-interface-clock mcbsp3_ick|clock-mcbsp4-ick@2ti,omap3-interface-clock mcbsp4_ick|emu_src_ckti,clkdm-gate-clock}1secure_32k_fck fixed-clockJ~gpt12_fckfixed-factor-clock~wdt1_fckfixed-factor-clock~security_l4_ick2fixed-factor-clockPclock@a14 ti,clksel +clock-aes1-ick@3ti,omap3-interface-clock aes1_ickclock-rng-ick@2ti,omap3-interface-clockrng_ickclock-sha11-ick@1ti,omap3-interface-clock sha11_ickclock-des1-ick@0ti,omap3-interface-clock des1_ickclock-pka-ick@4ti,omap3-interface-clockpka_ickclock@f00 ti,clksel+clock-cam-mclk@0ti,gate-clock cam_mclkclock-csi2-96m-fck@1ti,gate-clock csi2_96m_fckcam_ick@f10!ti,omap3-no-wait-interface-clockPZsecurity_l3_ickfixed-factor-clockNssi_l4_ickfixed-factor-clockPdsr_l4_ickfixed-factor-clockPdpll2_fck@40ti,divider-clock6Zg@rdpll2_ck@4ti,omap3-dpll-clock)$@4dpll2_m2_ck@44ti,divider-clockgDriva2_ck@0ti,wait-gate-clockZclock@a18 ti,clksel 2+clock-mad2d-ick@3ti,omap3-interface-clock mad2d_ickNclock-usbtll-ick@2ti,omap3-interface-clock usbtll_ickcssi_ssr_fck_3430es2ti,composite-clockssi_sst_fck_3430es2fixed-factor-clock sys_d2_ckfixed-factor-clock)Qomap_96m_d2_fckfixed-factor-clock`Romap_96m_d4_fckfixed-factor-clock`Somap_96m_d8_fckfixed-factor-clock`Tomap_96m_d10_fckfixed-factor-clock` Udpll5_m2_d4_ckfixed-factor-clockVdpll5_m2_d8_ckfixed-factor-clockWdpll5_m2_d16_ckfixed-factor-clockXdpll5_m2_d20_ckfixed-factor-clockYusim_fckti,composite-clockdpll5_ck@d04ti,omap3-dpll-clock))  $ L 4dpll5_m2_ck@d50ti,divider-clockg Prsgx_gate_fck@b00ti,composite-gate-clock6Z core_d3_ckfixed-factor-clock6core_d4_ckfixed-factor-clock6core_d6_ckfixed-factor-clock6omap_192m_alwon_fckfixed-factor-clock-core_d2_ckfixed-factor-clock6sgx_mux_fck@b40ti,composite-mux-clock : @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockN Zcpefuse_fck@a08ti,gate-clock) Zts_fck@a08ti,gate-clockO Zusbtll_fck@a08ti,wait-gate-clock Zdss_ick_3430es2@e10ti,omap3-dss-interface-clockPZusbhost_120m_fck@1400ti,gate-clockZusbhost_48m_fck@1400ti,dss-gate-clock@Zusbhost_ick@1410ti,omap3-dss-interface-clockPZclockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomain%dpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomain1dpll4_clkdmti,clockdomain'wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomaind2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsyscffckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intc H target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss # ? 'bick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma MX e`gpio@48310000ti,omap3-gpioH1gpio1r gpio@49050000ti,omap3-gpioIgpio2 gpio@49052000ti,omap3-gpioI gpio3 gpio@49054000ti,omap3-gpioI@ gpio4 gpio@49056000ti,omap3-gpioI`!gpio5 gpio@49058000ti,omap3-gpioI"gpio6 serial@4806a000ti,omap3-uartH H;12@txrxuart1Jlserial@4806c000ti,omap3-uartHI;34@txrxuart2Jlserial@49020000ti,omap3-uartIJ;56@txrxuart3Jlpdefault~i2c@48070000 ti,omap3-i2cH8+i2c1J'@twl@48H  ti,twl4030 pdefault~audioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2 vdd_ehciw@w@regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpio  twl4030-usbti,twl4030-usb %3AJ pwmti,twl4030-pwmUpwmledti,twl4030-pwmledUpwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad`pmadcti,twl4030-madci2c@48072000 ti,omap3-i2cH 9+i2c2 4disabledi2c@48060000 ti,omap3-i2cH=+i2c3Jpdefault~mailbox@48094000ti,omap3-mailboxmailboxH @mbox-dsp  spi@48098000ti,omap2-mcspiH A+mcspi1@;#$%&'()* @tx0rx0tx1rx1tx2rx2tx3rx3pdefault~spi@4809a000ti,omap2-mcspiH B+mcspi2 ;+,-.@tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 ;@tx0rx0tx1rx1pdefault~spi@480ba000ti,omap2-mcspiH 0+mcspi4;FG@tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1;=>@txrxpdefault~ %mmc@480b4000ti,omap3-hsmmcH @Vmmc2;/0@txrxpdefault~/%=mmc@480ad000ti,omap3-hsmmcH ^mmc3;MN@txrx 4disabledmmu@480bd400Pti,omap2-iommuH mmu_isp]mmu@5d000000Pti,omap2-iommu]mmu_iva 4disabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< mcommontxrx}mcbsp1; @txrxfck 4disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyss 'ick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?mcommontxrxsidetone}mcbsp2mcbsp2_sidetone;!"@txrxfckick4okaymcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZmcommontxrxsidetone}mcbsp3mcbsp3_sidetone;@txrxfckick4okaypdefault~mcbsp@49026000ti,omap3-mcbspI`mpu 67 mcommontxrx}mcbsp4;@txrxfck 4disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR mcommontxrx}mcbsp5;@txrxfck 4disabledsham@480c3000ti,omap3-shamshamH 0d1;E@rx 4disabledtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss ' 'fckick+ H1timer@0ti,omap3430-timerfck%Otarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss ' 'fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss ' 'fckick+ H0@timer@0ti,omap3430-timer_ usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3HDL'ehci@48064800 ti,ehci-omapHHM?gpmc@6e000000ti,omap3430-gpmcgpmcn;@rxtxDP+ 0 nand@0,0ti,omap2-nand   bqsw$$$0%4HEHV6e+x-loader@0 wX-Loaderbootloaders@80000wU-Bootbootloaders_env@260000 wU-Boot Env&kernel@280000wKernel(@filesystem@680000 wFile Systemhtarget-module@480ab000ti,sysc-omap2ti,syscH H H revsyscsyss  ? 'fck+ H usb@0ti,omap3-musb\]mmcdma}  ?  usb2-phyE2dss@48050000 ti,omap3-dssH4okay dss_corefck+pdefault~ dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll 4disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH 4disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  4disabled dss_vencfckportendpoint ssi-controller@48058000 ti,omap3-ssissi4okayHHsysgddGmgdd_mpu+   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+ 5Sisp@480bc000 ti,omap3-ispH H | lports+bandgap@48002524H%$ti,omap34xx-bandgaptarget-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $sysc fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $sysc fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap2ti,syscPrevfckick+ Pgpu@0#ti,omap3430-gpuimg,powervr-sgx530opp-tableoperating-points-v2-ti-cpu opp-125000000sY@  opp-250000000沀  g8g8g8*opp-500000000e  OOOopp-550000000 U  txtxtxopp-600000000#F  pppopp-720000000*T  ppp6thermal-zonescpu-thermalAWeN rtripscpu_alert8passivecpu_crit_ criticalcooling-mapsmap0 memory@80000000|memoryhsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z phsusb2-phy-pinsusb-nop-xceiv Jsoundti,omap-twl4030 omap3beagleregulator-mmc2-sdio-poweronregulator-fixedregulator-mmc2-sdio-poweron00 'gpio_poweroffpdefault~gpio-poweroff display panel-dpiwlcdpdefault~  portendpoint panel-timingJP   ( V " , 8  E O \ i sbacklightgpio-backlightpdefault~    compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesreg-namesti,sysc-maskti,sysc-sidleti,syss-maskstatusdmasdma-namesclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypass#ssize-cellsti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsti,pullupsti,pulldownsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplycd-gpiosbus-widthnon-removablecap-power-off-card#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsnand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,wr-access-nslabelmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicegpiostartup-delay-usreset-gpiosvcc-supplyti,modelti,mcbspenable-gpioshactivevactivehfront-porchhback-porchhsync-lenvback-porchvfront-porchvsync-lenhsync-activevsync-activede-activepixelclk-activedefault-on