8( 'l)isee,omap3-igep0030ti,omap3630ti,omap3 +*7IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)chosen=/ocp@68000000/serial@49020000aliasesI/ocp@68000000/i2c@48070000N/ocp@68000000/i2c@48072000S/ocp@68000000/i2c@48060000X/ocp@68000000/mmc@4809c000]/ocp@68000000/mmc@480b4000b/ocp@68000000/mmc@480ad000g/ocp@68000000/serial@4806a000o/ocp@68000000/serial@4806c000w/ocp@68000000/serial@49020000/ocp@68000000/serial@49042000cpus+cpu@0arm,cortex-a8cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus +  pinmux@30 ti,omap3-padconfpinctrl-single08+ *?]zdefaultgpmc-pinsuart1-pinsRLuart3-pinsnpmcbsp2-pins  mmc1-pins0mmc2-pins0(*,.02i2c1-pinsi2c3-pinstwl4030-pinsAhsusb2-pins0      uart2-pins <>@Blbee1usjyc-pins68:scm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselh+clock-mcbsp5-mux-fck@4ti,composite-mux-clockmcbsp5_mux_fck clock-mcbsp3-mux-fck@0ti,composite-mux-clockmcbsp3_mux_fck clock-mcbsp4-mux-fck@2ti,composite-mux-clockmcbsp4_mux_fck mcbsp5_fckti,composite-clock clock@4 ti,clksel+clock-mcbsp1-mux-fck@2ti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fck@6ti,composite-mux-clockmcbsp2_mux_fck mcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clockmcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ *?]twl4030-vpins-pins target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `L revsyscsyss #1ick+ H ` aes1@0 ti,omap3-aesP>  Ctxrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PL revsyscsyss #1ick+ H P aes2@0 ti,omap3-aesP>ABCtxrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockMYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clock]jpu"sys_clkout1@d70ti,gate-clock p]dpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock!dpll4_x2_ckfixed-factor-clock corex2_fckfixed-factor-clock!#wkup_l4_ickfixed-factor-clock"bcorex2_d3_fckfixed-factor-clock#corex2_d5_fckfixed-factor-clock#clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockMomap_32k_fck fixed-clockMHvirt_12m_ck fixed-clockMvirt_13m_ck fixed-clockM]@virt_19200000_ck fixed-clockM$virt_26000000_ck fixed-clockMvirt_38_4m_ck fixed-clockMIdpll4_ck@d00ti,omap3-dpll-per-j-type-clock"" D 0 dpll4_m2_ck@d48ti,divider-clock j? Hu$dpll4_m2x2_mul_ckfixed-factor-clock$%dpll4_m2x2_ck@d00ti,hsdiv-gate-clock%] &omap_96m_alwon_fckfixed-factor-clock&2dpll3_ck@d00ti,omap3-dpll-core-clock"" @ 0clock@1140 ti,clksel@+clock-dpll3-m3@16ti,divider-clock dpll3_m3_ckju,clock-dpll4-m6@24ti,divider-clock dpll4_m6_ck j?u>clock-emu-src-mux@0 ti,mux-clockemu_src_mux_ck"'()vclock-pclk-fck@8ti,divider-clock pclk_fck*juclock-pclkx2-fck@6ti,divider-clock pclkx2_fck*juclock-atclk-fck@4ti,divider-clock atclk_fck*juclock-traceclk-src-fck@2 ti,mux-clocktraceclk_src_fck"'()+clock-traceclk-fck@11 ti,divider-clock traceclk_fck+judpll3_m3x2_mul_ckfixed-factor-clock,-dpll3_m3x2_ck@d00ti,hsdiv-gate-clock-]  .emu_core_alwon_ckfixed-factor-clock.'sys_altclk fixed-clockM5mcbsp_clks fixed-clockMcore_ckfixed-factor-clock/dpll1_fck@940ti,divider-clock/]j @u0dpll1_ck@904ti,omap3-dpll-clock"0  $ @ 4dpll1_x2_ckfixed-factor-clock1dpll1_x2m2_ck@944ti,divider-clock1j DuEcm_96m_fckfixed-factor-clock23clock@d40 ti,clksel @+clock-dpll3-m2@27ti,divider-clock dpll3_m2_ckjuclock-omap-96m-fck@6 ti,mux-clock omap_96m_fck3"Yclock-omap-54m-fck@5 ti,mux-clock omap_54m_fck45Aclock-omap-48m-fck@3 ti,mux-clock omap_48m_fck659clock@e40 ti,clksel@+clock-dpll4-m3@8ti,divider-clock dpll4_m3_ck j u7clock-dpll4-m4@0ti,divider-clock dpll4_m4_ck ju:dpll4_m3x2_mul_ckfixed-factor-clock78dpll4_m3x2_ck@d00ti,hsdiv-gate-clock8] 4cm_96m_d2_fckfixed-factor-clock36omap_12m_fckfixed-factor-clock9Zdpll4_m4x2_mul_ckti,fixed-factor-clock:;dpll4_m4x2_ck@d00ti,gate-clock;] ^dpll4_m5_ck@f40ti,divider-clock j?@u<dpll4_m5x2_mul_ckti,fixed-factor-clock<=dpll4_m5x2_ck@d00ti,hsdiv-gate-clock=] zdpll4_m6x2_mul_ckfixed-factor-clock>?dpll4_m6x2_ck@d00ti,hsdiv-gate-clock?] @emu_per_alwon_ckfixed-factor-clock@(clock@d70 ti,clksel p+clock-clkout2-src-gate@7 ti,composite-no-wait-gate-clockclkout2_src_gate_ck/Cclock-clkout2-src-mux@0ti,composite-mux-clockclkout2_src_mux_ck/"3ADclock-sys-clkout2@3ti,divider-clock sys_clkout2Bj@clkout2_src_ckti,composite-clockCDBmpu_ckfixed-factor-clockEFarm_fck@924ti,divider-clockF $jemu_mpu_alwon_ckfixed-factor-clockF)clock@a40 ti,clksel @+clock-l3-ick@0ti,divider-clockl3_ick/juGclock-l4-ick@2ti,divider-clockl4_ickGjuIclock-gpt10-mux-fck@6ti,composite-mux-clockgpt10_mux_fckH"Vclock-gpt11-mux-fck@7ti,composite-mux-clockgpt11_mux_fckH"Xclock-ssi-ssr-div-fck-3430es2@8ti,composite-divider-clockssi_ssr_div_fck_3430es2#$clock@c40 ti,clksel @+clock-rm-ick@1ti,divider-clockrm_ickIjuclock-gpt1-mux-fck@0ti,composite-mux-clock gpt1_mux_fckH"aclock-usim-mux-fck@3ti,composite-mux-clock usim_mux_fck("JKLMNOPQRuclock@a00 ti,clksel +clock-gpt10-gate-fck@11 ti,composite-gate-clockgpt10_gate_fck"Uclock-gpt11-gate-fck@12 ti,composite-gate-clockgpt11_gate_fck"Wclock-mmchs2-fck@25ti,wait-gate-clock mmchs2_fckclock-mmchs1-fck@24ti,wait-gate-clock mmchs1_fckclock-i2c3-fck@17ti,wait-gate-clock i2c3_fckclock-i2c2-fck@16ti,wait-gate-clock i2c2_fckclock-i2c1-fck@15ti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fck@10 ti,composite-gate-clockmcbsp5_gate_fck clock-mcbsp1-gate-fck@9 ti,composite-gate-clockmcbsp1_gate_fck clock-mcspi4-fck@21ti,wait-gate-clock mcspi4_fckSclock-mcspi3-fck@20ti,wait-gate-clock mcspi3_fckSclock-mcspi2-fck@19ti,wait-gate-clock mcspi2_fckSclock-mcspi1-fck@18ti,wait-gate-clock mcspi1_fckSclock-uart2-fck@14ti,wait-gate-clock uart2_fckSclock-uart1-fck@13 ti,wait-gate-clock uart1_fckSclock-hdq-fck@22ti,wait-gate-clockhdq_fckTclock-modem-fck@31ti,omap3-interface-clock modem_fck"clock-mspro-fck@23ti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2@0 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2#~clock-mmchs3-fck@30ti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockUVgpt11_fckti,composite-clockWXcore_96m_fckfixed-factor-clockYcore_48m_fckfixed-factor-clock9Score_12m_fckfixed-factor-clockZTcore_l3_ickfixed-factor-clockG[clock@a10 ti,clksel +clock-sdrc-ick@1ti,wait-gate-clock sdrc_ick[clock-mmchs2-ick@25ti,omap3-interface-clock mmchs2_ick\clock-mmchs1-ick@24ti,omap3-interface-clock mmchs1_ick\clock-hdq-ick@22ti,omap3-interface-clockhdq_ick\clock-mcspi4-ick@21ti,omap3-interface-clock mcspi4_ick\clock-mcspi3-ick@20ti,omap3-interface-clock mcspi3_ick\clock-mcspi2-ick@19ti,omap3-interface-clock mcspi2_ick\clock-mcspi1-ick@18ti,omap3-interface-clock mcspi1_ick\clock-i2c3-ick@17ti,omap3-interface-clock i2c3_ick\clock-i2c2-ick@16ti,omap3-interface-clock i2c2_ick\clock-i2c1-ick@15ti,omap3-interface-clock i2c1_ick\clock-uart2-ick@14ti,omap3-interface-clock uart2_ick\clock-uart1-ick@13 ti,omap3-interface-clock uart1_ick\clock-gpt11-ick@12 ti,omap3-interface-clock gpt11_ick\clock-gpt10-ick@11 ti,omap3-interface-clock gpt10_ick\clock-mcbsp5-ick@10 ti,omap3-interface-clock mcbsp5_ick\clock-mcbsp1-ick@9 ti,omap3-interface-clock mcbsp1_ick\clock-omapctrl-ick@6ti,omap3-interface-clock omapctrl_ick\clock-aes2-ick@28ti,omap3-interface-clock aes2_ick\clock-sha12-ick@27ti,omap3-interface-clock sha12_ick\clock-icr-ick@29ti,omap3-interface-clockicr_ick\clock-des2-ick@26ti,omap3-interface-clock des2_ick\clock-mspro-ick@23ti,omap3-interface-clock mspro_ick\clock-mailboxes-ick@7ti,omap3-interface-clockmailboxes_ick\clock-sad2d-ick@3ti,omap3-interface-clock sad2d_ickGclock-hsotgusb-ick-3430es2@4"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2[clock-ssi-ick-3430es2@0ti,omap3-ssi-interface-clockssi_ick_3430es2] clock-mmchs3-ick@30ti,omap3-interface-clock mmchs3_ick\gpmc_fckfixed-factor-clock[core_l4_ickfixed-factor-clockI\clock@e00 ti,clksel+clock-dss-tv-fckti,gate-clock dss_tv_fckA]clock-dss-96m-fckti,gate-clock dss_96m_fckY]clock-dss2-alwon-fckti,gate-clockdss2_alwon_fck"]clock-dss1-alwon-fck-3430es2@0ti,dss-gate-clockdss1_alwon_fck_3430es2^dummy_ck fixed-clockMclock@c00 ti,clksel +clock-gpt1-gate-fck@0ti,composite-gate-clockgpt1_gate_fck"`clock-gpio1-dbck@3ti,gate-clock gpio1_dbck_clock-wdt2-fck@5ti,wait-gate-clock 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ti,clksel@+clock-gpt2-mux-fck@0ti,composite-mux-clock gpt2_mux_fckH"fclock-gpt3-mux-fck@1ti,composite-mux-clock gpt3_mux_fckH"hclock-gpt4-mux-fck@2ti,composite-mux-clock gpt4_mux_fckH"jclock-gpt5-mux-fck@3ti,composite-mux-clock gpt5_mux_fckH"lclock-gpt6-mux-fck@4ti,composite-mux-clock gpt6_mux_fckH"nclock-gpt7-mux-fck@5ti,composite-mux-clock gpt7_mux_fckH"pclock-gpt8-mux-fck@6ti,composite-mux-clock gpt8_mux_fckH"rclock-gpt9-mux-fck@7ti,composite-mux-clock gpt9_mux_fckH"tgpt2_fckti,composite-clockefgpt3_fckti,composite-clockghgpt4_fckti,composite-clockijgpt5_fckti,composite-clockklgpt6_fckti,composite-clockmngpt7_fckti,composite-clockopgpt8_fckti,composite-clockqrgpt9_fckti,composite-clockstper_32k_alwon_fckfixed-factor-clockHdper_l4_ickfixed-factor-clockIuclock@1010 ti,clksel+clock-gpio6-ick@17ti,omap3-interface-clock gpio6_ickuclock-gpio5-ick@16ti,omap3-interface-clock gpio5_ickuclock-gpio4-ick@15ti,omap3-interface-clock gpio4_ickuclock-gpio3-ick@14ti,omap3-interface-clock gpio3_ickuclock-gpio2-ick@13 ti,omap3-interface-clock gpio2_ickuclock-wdt3-ick@12 ti,omap3-interface-clock wdt3_ickuclock-uart3-ick@11 ti,omap3-interface-clock uart3_ickuclock-uart4-ick@18ti,omap3-interface-clock uart4_ickuclock-gpt9-ick@10 ti,omap3-interface-clock gpt9_ickuclock-gpt8-ick@9 ti,omap3-interface-clock gpt8_ickuclock-gpt7-ick@8ti,omap3-interface-clock gpt7_ickuclock-gpt6-ick@7ti,omap3-interface-clock gpt6_ickuclock-gpt5-ick@6ti,omap3-interface-clock gpt5_ickuclock-gpt4-ick@5ti,omap3-interface-clock gpt4_ickuclock-gpt3-ick@4ti,omap3-interface-clock gpt3_ickuclock-gpt2-ick@3ti,omap3-interface-clock gpt2_ickuclock-mcbsp2-ick@0ti,omap3-interface-clock mcbsp2_ickuclock-mcbsp3-ick@1ti,omap3-interface-clock mcbsp3_ickuclock-mcbsp4-ick@2ti,omap3-interface-clock mcbsp4_ickuemu_src_ckti,clkdm-gate-clockv*secure_32k_fck fixed-clockMwgpt12_fckfixed-factor-clockwwdt1_fckfixed-factor-clockwsecurity_l4_ick2fixed-factor-clockIxclock@a14 ti,clksel +clock-aes1-ick@3ti,omap3-interface-clock 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wkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomain|d2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2  revsysc#_fckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intc*H target-module@48056000ti,sysc-omap2ti,syscH`H`,H`( revsyscsyss# B #1[ick+ H`dma-controller@0ti,omap3630-sdmati,omap-sdma P[ h`gpio@48310000ti,omap3-gpioH1gpio1u*gpio@49050000ti,omap3-gpioIgpio2*gpio@49052000ti,omap3-gpioI gpio3*gpio@49054000ti,omap3-gpioI@ gpio4*gpio@49056000ti,omap3-gpioI`!gpio5*gpio@49058000ti,omap3-gpioI"gpio6*serial@4806a000ti,omap3-uartH H>12Ctxrxuart1Mlzdefaultserial@4806c000ti,omap3-uartHI>34Ctxrxuart2Mlzdefaultserial@49020000ti,omap3-uartIJ>56Ctxrxuart3Mlzdefaulti2c@48070000 ti,omap3-i2cH8+i2c1zdefaultM'@twl@48H  ti,twl4030*zdefaultaudioti,twl4030-audiocodecrtcti,twl4030-rtc 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FcommontxrxVmcbsp5>Ctxrxfck "disabledsham@480c3000ti,omap3-shamshamH 0d1>ECrxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1 revsyscsyss' #1fckick+ H1vtimer@0ti,omap3430-timerfck%Htarget-module@49032000ti,sysc-omap2-timerti,syscI I I  revsyscsyss' #1fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@ revsyscsyss' #1fckick+ H0@timer@0ti,omap3430-timer_usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyohci@48064400ti,ohci-omap3HDLehci@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcn>Crxtx)+*zdefault0nand@0,0ti,omap2-nand  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compatibleinterrupt-parent#address-cells#size-cellsmodelstdout-pathi2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2serial3device_typeregclocksclock-namesclock-latencyoperating-points-v2vbb-supply#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypass#ssize-cellsti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cells#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplyvmmc_aux-supplybus-widthcd-gpiosmmc-pwrseqnon-removablestatus#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nsgpmc,sync-readgpmc,sync-writegpmc,burst-lengthgpmc,burst-wrapgpmc,burst-readgpmc,burst-writegpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowerti,tranxdone-status-maskti,settling-timeti,clock-cyclesti,abb_infoiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendti,absolute-max-voltage-uvpolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-deviceti,modelti,mcbspregulator-always-onlabeldefault-statereset-gpios