8 @( E Egumstix,omap3-overo-tobiduogumstix,omap3-overoti,omap3430ti,omap3 +"7OMAP35xx Gumstix Overo on TobiDuochosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000cpus+cpu@0arm,cortex-a8scpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+  >[defaultiuart2-pins s<>@Bi2c1-pinssmmc1-pins0smmc2-pins0s(*,.02w3cbw003c-pinsslhsusb2-pins@s      twl4030-pinssAi2c3-pinssuart3-pinssnpscm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselh+clock-mcbsp5-mux-fck@4ti,composite-mux-clockmcbsp5_mux_fck clock-mcbsp3-mux-fck@0ti,composite-mux-clockmcbsp3_mux_fckclock-mcbsp4-mux-fck@2ti,composite-mux-clockmcbsp4_mux_fckmcbsp5_fckti,composite-clock clock@4 ti,clksel+clock-mcbsp1-mux-fck@2ti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fck@6ti,composite-mux-clockmcbsp2_mux_fckmcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clock mcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+  >twl4030-vpins-pins starget-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss ick+ H ` aes1@0 ti,omap3-aesP  $txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss ick+ H P aes2@0 ti,omap3-aesPAB$txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clock.Yosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clock>KpV!sys_clkout1@d70ti,gate-clock p>dpll3_x2_ckfixed-factor-clockmxdpll3_m2x2_ckfixed-factor-clockmx dpll4_x2_ckfixed-factor-clockmxcorex2_fckfixed-factor-clock mx"wkup_l4_ickfixed-factor-clock!mxacorex2_d3_fckfixed-factor-clock"mxcorex2_d5_fckfixed-factor-clock"mxclockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clock.omap_32k_fck fixed-clock.Gvirt_12m_ck fixed-clock.virt_13m_ck fixed-clock.]@virt_19200000_ck fixed-clock.$virt_26000000_ck fixed-clock.virt_38_4m_ck fixed-clock.Idpll4_ck@d00ti,omap3-dpll-per-clock!! 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sys_clkout2AK@clkout2_src_ckti,composite-clockBCAmpu_ckfixed-factor-clockDmxEarm_fck@924ti,divider-clockE $Kemu_mpu_alwon_ckfixed-factor-clockEmx(clock@a40 ti,clksel @+clock-l3-ick@0ti,divider-clockl3_ick.KVFclock-l4-ick@2ti,divider-clockl4_ickFKVHclock-gpt10-mux-fck@6ti,composite-mux-clockgpt10_mux_fckG!Uclock-gpt11-mux-fck@7ti,composite-mux-clockgpt11_mux_fckG!Wclock-ssi-ssr-div-fck-3430es2@8ti,composite-divider-clockssi_ssr_div_fck_3430es2"$~clock@c40 ti,clksel @+clock-rm-ick@1ti,divider-clockrm_ickHKVclock-gpt1-mux-fck@0ti,composite-mux-clock gpt1_mux_fckG!`clock-usim-mux-fck@3ti,composite-mux-clock usim_mux_fck(!IJKLMNOPQVclock@a00 ti,clksel +clock-gpt10-gate-fck@11 ti,composite-gate-clockgpt10_gate_fck!Tclock-gpt11-gate-fck@12 ti,composite-gate-clockgpt11_gate_fck!Vclock-mmchs2-fck@25ti,wait-gate-clock mmchs2_fckclock-mmchs1-fck@24ti,wait-gate-clock mmchs1_fckclock-i2c3-fck@17ti,wait-gate-clock i2c3_fckclock-i2c2-fck@16ti,wait-gate-clock i2c2_fckclock-i2c1-fck@15ti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fck@10 ti,composite-gate-clockmcbsp5_gate_fck clock-mcbsp1-gate-fck@9 ti,composite-gate-clockmcbsp1_gate_fck clock-mcspi4-fck@21ti,wait-gate-clock mcspi4_fckRclock-mcspi3-fck@20ti,wait-gate-clock mcspi3_fckRclock-mcspi2-fck@19ti,wait-gate-clock mcspi2_fckRclock-mcspi1-fck@18ti,wait-gate-clock mcspi1_fckRclock-uart2-fck@14ti,wait-gate-clock uart2_fckRclock-uart1-fck@13 ti,wait-gate-clock uart1_fckRclock-hdq-fck@22ti,wait-gate-clockhdq_fckSclock-modem-fck@31ti,omap3-interface-clock modem_fck!clock-mspro-fck@23ti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2@0 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2"}clock-mmchs3-fck@30ti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockTUgpt11_fckti,composite-clockVWcore_96m_fckfixed-factor-clockXmxcore_48m_fckfixed-factor-clock8mxRcore_12m_fckfixed-factor-clockYmxScore_l3_ickfixed-factor-clockFmxZclock@a10 ti,clksel +clock-sdrc-ick@1ti,wait-gate-clock sdrc_ickZclock-mmchs2-ick@25ti,omap3-interface-clock mmchs2_ick[clock-mmchs1-ick@24ti,omap3-interface-clock mmchs1_ick[clock-hdq-ick@22ti,omap3-interface-clockhdq_ick[clock-mcspi4-ick@21ti,omap3-interface-clock mcspi4_ick[clock-mcspi3-ick@20ti,omap3-interface-clock mcspi3_ick[clock-mcspi2-ick@19ti,omap3-interface-clock mcspi2_ick[clock-mcspi1-ick@18ti,omap3-interface-clock mcspi1_ick[clock-i2c3-ick@17ti,omap3-interface-clock i2c3_ick[clock-i2c2-ick@16ti,omap3-interface-clock i2c2_ick[clock-i2c1-ick@15ti,omap3-interface-clock i2c1_ick[clock-uart2-ick@14ti,omap3-interface-clock uart2_ick[clock-uart1-ick@13 ti,omap3-interface-clock uart1_ick[clock-gpt11-ick@12 ti,omap3-interface-clock gpt11_ick[clock-gpt10-ick@11 ti,omap3-interface-clock gpt10_ick[clock-mcbsp5-ick@10 ti,omap3-interface-clock mcbsp5_ick[clock-mcbsp1-ick@9 ti,omap3-interface-clock mcbsp1_ick[clock-omapctrl-ick@6ti,omap3-interface-clock omapctrl_ick[clock-aes2-ick@28ti,omap3-interface-clock aes2_ick[clock-sha12-ick@27ti,omap3-interface-clock sha12_ick[clock-icr-ick@29ti,omap3-interface-clockicr_ick[clock-des2-ick@26ti,omap3-interface-clock des2_ick[clock-mspro-ick@23ti,omap3-interface-clock mspro_ick[clock-mailboxes-ick@7ti,omap3-interface-clockmailboxes_ick[clock-sad2d-ick@3ti,omap3-interface-clock sad2d_ickFclock-hsotgusb-ick-3430es2@4"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2Zclock-ssi-ick-3430es2@0ti,omap3-ssi-interface-clockssi_ick_3430es2\ clock-mmchs3-ick@30ti,omap3-interface-clock mmchs3_ick[gpmc_fckfixed-factor-clockZmxcore_l4_ickfixed-factor-clockHmx[clock@e00 ti,clksel+clock-dss-tv-fckti,gate-clock dss_tv_fck@>clock-dss-96m-fckti,gate-clock dss_96m_fckX>clock-dss2-alwon-fckti,gate-clockdss2_alwon_fck!>clock-dss1-alwon-fck-3430es2@0ti,dss-gate-clockdss1_alwon_fck_3430es2]dummy_ck fixed-clock.clock@c00 ti,clksel +clock-gpt1-gate-fck@0ti,composite-gate-clockgpt1_gate_fck!_clock-gpio1-dbck@3ti,gate-clock gpio1_dbck^clock-wdt2-fck@5ti,wait-gate-clock wdt2_fck^clock-sr1-fck@6ti,wait-gate-clocksr1_fck! clock-sr2-fck@7ti,wait-gate-clocksr2_fck! clock-usim-gate-fck@9 ti,composite-gate-clockusim_gate_fckXgpt1_fckti,composite-clock_`wkup_32k_fckfixed-factor-clockGmx^clock@c10 ti,clksel +clock-wdt2-ick@5ti,omap3-interface-clock wdt2_ickaclock-wdt1-ick@4ti,omap3-interface-clock wdt1_ickaclock-gpio1-ick@3ti,omap3-interface-clock gpio1_ickaclock-omap-32ksync-ick@2ti,omap3-interface-clockomap_32ksync_ickaclock-gpt12-ick@1ti,omap3-interface-clock gpt12_ickaclock-gpt1-ick@0ti,omap3-interface-clock gpt1_ickaclock-usim-ick@9 ti,omap3-interface-clock usim_ickaper_96m_fckfixed-factor-clock1mxper_48m_fckfixed-factor-clock8mxbclock@1000 ti,clksel+clock-uart3-fck@11 ti,wait-gate-clock uart3_fckbclock-gpt2-gate-fck@3ti,composite-gate-clockgpt2_gate_fck!dclock-gpt3-gate-fck@4ti,composite-gate-clockgpt3_gate_fck!fclock-gpt4-gate-fck@5ti,composite-gate-clockgpt4_gate_fck!hclock-gpt5-gate-fck@6ti,composite-gate-clockgpt5_gate_fck!jclock-gpt6-gate-fck@7ti,composite-gate-clockgpt6_gate_fck!lclock-gpt7-gate-fck@8ti,composite-gate-clockgpt7_gate_fck!nclock-gpt8-gate-fck@9 ti,composite-gate-clockgpt8_gate_fck!pclock-gpt9-gate-fck@10 ti,composite-gate-clockgpt9_gate_fck!rclock-gpio6-dbck@17ti,gate-clock gpio6_dbckcclock-gpio5-dbck@16ti,gate-clock gpio5_dbckcclock-gpio4-dbck@15ti,gate-clock gpio4_dbckcclock-gpio3-dbck@14ti,gate-clock gpio3_dbckcclock-gpio2-dbck@13 ti,gate-clock gpio2_dbckcclock-wdt3-fck@12 ti,wait-gate-clock wdt3_fckcclock-mcbsp2-gate-fck@0ti,composite-gate-clockmcbsp2_gate_fck clock-mcbsp3-gate-fck@1ti,composite-gate-clockmcbsp3_gate_fckclock-mcbsp4-gate-fck@2ti,composite-gate-clockmcbsp4_gate_fckclock@1040 ti,clksel@+clock-gpt2-mux-fck@0ti,composite-mux-clock gpt2_mux_fckG!eclock-gpt3-mux-fck@1ti,composite-mux-clock gpt3_mux_fckG!gclock-gpt4-mux-fck@2ti,composite-mux-clock gpt4_mux_fckG!iclock-gpt5-mux-fck@3ti,composite-mux-clock gpt5_mux_fckG!kclock-gpt6-mux-fck@4ti,composite-mux-clock gpt6_mux_fckG!mclock-gpt7-mux-fck@5ti,composite-mux-clock gpt7_mux_fckG!oclock-gpt8-mux-fck@6ti,composite-mux-clock gpt8_mux_fckG!qclock-gpt9-mux-fck@7ti,composite-mux-clock gpt9_mux_fckG!sgpt2_fckti,composite-clockdegpt3_fckti,composite-clockfggpt4_fckti,composite-clockhigpt5_fckti,composite-clockjkgpt6_fckti,composite-clocklmgpt7_fckti,composite-clocknogpt8_fckti,composite-clockpqgpt9_fckti,composite-clockrsper_32k_alwon_fckfixed-factor-clockGmxcper_l4_ickfixed-factor-clockHmxtclock@1010 ti,clksel+clock-gpio6-ick@17ti,omap3-interface-clock gpio6_icktclock-gpio5-ick@16ti,omap3-interface-clock gpio5_icktclock-gpio4-ick@15ti,omap3-interface-clock gpio4_icktclock-gpio3-ick@14ti,omap3-interface-clock gpio3_icktclock-gpio2-ick@13 ti,omap3-interface-clock gpio2_icktclock-wdt3-ick@12 ti,omap3-interface-clock wdt3_icktclock-uart3-ick@11 ti,omap3-interface-clock uart3_icktclock-uart4-ick@18ti,omap3-interface-clock uart4_icktclock-gpt9-ick@10 ti,omap3-interface-clock gpt9_icktclock-gpt8-ick@9 ti,omap3-interface-clock gpt8_icktclock-gpt7-ick@8ti,omap3-interface-clock gpt7_icktclock-gpt6-ick@7ti,omap3-interface-clock gpt6_icktclock-gpt5-ick@6ti,omap3-interface-clock gpt5_icktclock-gpt4-ick@5ti,omap3-interface-clock gpt4_icktclock-gpt3-ick@4ti,omap3-interface-clock gpt3_icktclock-gpt2-ick@3ti,omap3-interface-clock gpt2_icktclock-mcbsp2-ick@0ti,omap3-interface-clock mcbsp2_icktclock-mcbsp3-ick@1ti,omap3-interface-clock mcbsp3_icktclock-mcbsp4-ick@2ti,omap3-interface-clock mcbsp4_icktemu_src_ckti,clkdm-gate-clocku)secure_32k_fck fixed-clock.vgpt12_fckfixed-factor-clockvmxwdt1_fckfixed-factor-clockvmxsecurity_l4_ick2fixed-factor-clockHmxwclock@a14 ti,clksel +clock-aes1-ick@3ti,omap3-interface-clock aes1_ickwclock-rng-ick@2ti,omap3-interface-clockrng_ickwclock-sha11-ick@1ti,omap3-interface-clock sha11_ickwclock-des1-ick@0ti,omap3-interface-clock des1_ickwclock-pka-ick@4ti,omap3-interface-clockpka_ickxclock@f00 ti,clksel+clock-cam-mclk@0ti,gate-clock cam_mclkyclock-csi2-96m-fck@1ti,gate-clock csi2_96m_fckcam_ick@f10!ti,omap3-no-wait-interface-clockH>security_l3_ickfixed-factor-clockFmxxssi_l4_ickfixed-factor-clockHmx\sr_l4_ickfixed-factor-clockHmxdpll2_fck@40ti,divider-clock.>K@Vzdpll2_ck@4ti,omap3-dpll-clock!z$@4{dpll2_m2_ck@44ti,divider-clock{KDV|iva2_ck@0ti,wait-gate-clock|>clock@a18 ti,clksel +clock-mad2d-ick@3ti,omap3-interface-clock mad2d_ickFclock-usbtll-ick@2ti,omap3-interface-clock usbtll_ick[ssi_ssr_fck_3430es2ti,composite-clock}~ssi_sst_fck_3430es2fixed-factor-clockmxsys_d2_ckfixed-factor-clock!mxIomap_96m_d2_fckfixed-factor-clockXmxJomap_96m_d4_fckfixed-factor-clockXmxKomap_96m_d8_fckfixed-factor-clockXmxLomap_96m_d10_fckfixed-factor-clockXmx Mdpll5_m2_d4_ckfixed-factor-clockmxNdpll5_m2_d8_ckfixed-factor-clockmxOdpll5_m2_d16_ckfixed-factor-clockmxPdpll5_m2_d20_ckfixed-factor-clockmxQusim_fckti,composite-clockdpll5_ck@d04ti,omap3-dpll-clock!!  $ L 4dpll5_m2_ck@d50ti,divider-clockK PVsgx_gate_fck@b00ti,composite-gate-clock.> core_d3_ckfixed-factor-clock.mxcore_d4_ckfixed-factor-clock.mxcore_d6_ckfixed-factor-clock.mxomap_192m_alwon_fckfixed-factor-clock%mxcore_d2_ckfixed-factor-clock.mxsgx_mux_fck@b40ti,composite-mux-clock 2 @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockF >cpefuse_fck@a08ti,gate-clock! >ts_fck@a08ti,gate-clockG >usbtll_fck@a08ti,wait-gate-clock >dss_ick_3430es2@e10ti,omap3-dss-interface-clockH>usbhost_120m_fck@1400ti,gate-clock>usbhost_48m_fck@1400ti,dss-gate-clock8>usbhost_ick@1410ti,omap3-dss-interface-clockH>clockdomainscore_l3_clkdmti,clockdomaindpll3_clkdmti,clockdomaindpll1_clkdmti,clockdomainper_clkdmti,clockdomainhemu_clkdmti,clockdomain)dpll4_clkdmti,clockdomainwkup_clkdmti,clockdomain$dss_clkdmti,clockdomaincore_l4_clkdmti,clockdomaincam_clkdmti,clockdomainiva2_clkdmti,clockdomaindpll2_clkdmti,clockdomain{d2d_clkdmti,clockdomain dpll5_clkdmti,clockdomainsgx_clkdmti,clockdomainusbhost_clkdmti,clockdomain target-module@48320000ti,sysc-omap2ti,syscH2H2 revsysc^fckick+ H2counter@0ti,omap-counter32k interrupt-controller@48200000ti,omap3-intc H target-module@48056000ti,sysc-omap2ti,syscH`H`,H`(revsyscsyss# # Zick+ H`dma-controller@0ti,omap3430-sdmati,omap-sdma 1< I`gpio@48310000ti,omap3-gpioH1gpio1Vhx gpio@49050000ti,omap3-gpioIgpio2hx gpio@49052000ti,omap3-gpioI gpio3hx gpio@49054000ti,omap3-gpioI@ gpio4hx gpio@49056000ti,omap3-gpioI`!gpio5hx gpio@49058000ti,omap3-gpioI"gpio6hx serial@4806a000ti,omap3-uartH H12$txrxuart1.lserial@4806c000ti,omap3-uartHI34$txrxuart2.l[defaultiserial@49020000ti,omap3-uartIJn56$txrxuart3.l[defaultii2c@48070000 ti,omap3-i2cH8+i2c1[defaulti.'@twl@48H  ti,twl4030 [defaultiaudioti,twl4030-audiocodecrtcti,twl4030-rtc bciti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' regulator-vdacti,twl4030-vdacw@w@regulator-vioti,twl4030-vioregulator-vintana1ti,twl4030-vintana1regulator-vintana2ti,twl4030-vintana2regulator-vintdigti,twl4030-vintdigregulator-vmmc1ti,twl4030-vmmc1:0regulator-vmmc2ti,twl4030-vmmc2:0regulator-vusb1v5ti,twl4030-vusb1v5regulator-vusb1v8ti,twl4030-vusb1v8regulator-vusb3v1ti,twl4030-vusb3v1regulator-vpll1ti,twl4030-vpll1regulator-vpll2ti,twl4030-vpll2w@w@regulator-vsimti,twl4030-vsimw@-gpioti,twl4030-gpiohx twl4030-usbti,twl4030-usb pwmti,twl4030-pwm pwmledti,twl4030-pwmled pwrbuttonti,twl4030-pwrbuttonkeypadti,twl4030-keypad(madcti,twl4030-madc;i2c@48072000 ti,omap3-i2cH 9+i2c2 Mdisabledi2c@48060000 ti,omap3-i2cH=+i2c3[defaulti.eeprom@51 atmel,24c01QTlis33de@1dst,lis33dest,lis3lv02d]hv    +:IXxgxv&& Mdisabledmailbox@48094000ti,omap3-mailboxmailboxH @mbox-dsp  spi@48098000ti,omap2-mcspiH A+mcspi1@#$%&'()* $tx0rx0tx1rx1tx2rx2tx3rx3spi@4809a000ti,omap2-mcspiH B+mcspi2 +,-.$tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 $tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi4FG$tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc1=>$txrx[defaulti ,mmc@480b4000ti,omap3-hsmmcH @Vmmc2/0$txrx[defaulti 6,CPmmc@480ad000ti,omap3-hsmmcH ^mmc3MN$txrx Mdisabledmmu@480bd400^ti,omap2-iommuH mmu_ispk mmu@5d000000^ti,omap2-iommu]mmu_iva Mdisabledwdt@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< {commontxrxmcbsp1 $txrxfck Mdisabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyssick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?{commontxrxsidetonemcbsp2mcbsp2_sidetone!"$txrxfckickMokaymcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZ{commontxrxsidetonemcbsp3mcbsp3_sidetone$txrxfckick Mdisabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 {commontxrxmcbsp4$txrxfck Mdisabledmcbsp@48096000ti,omap3-mcbspH `mpu QR {commontxrxmcbsp5$txrxfck Mdisabledsham@480c3000ti,omap3-shamshamH 0d1E$rxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss' fckick+ H1timer@0ti,omap3430-timerfck%Gtarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss' fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8 timer@49040000ti,omap3430-timerI-timer9 timer@48086000ti,omap3430-timerH`.timer10 timer@48088000ti,omap3430-timerH/timer11 target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss' fckick+ H0@timer@0ti,omap3430-timer_usbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ *ehci-phyohci@48064400ti,ohci-omap3HDL5ehci@48064800 ti,ehci-omapHHMMgpmc@6e000000ti,omap3430-gpmcgpmcn$rxtxR^+ hx00+,nand@0,0ti,omap2-nandpmicron,mt29c4g96maz  bch8,,",((76F@URfRw(+partition@0SPLpartition@80000U-Bootpartition@1c0000 Environment$partition@280000Kernel(partition@780000 Filesystemethernet@gpmcsmsc,lan9221smsc,lan9115*$  7*($U<f6F$ w* + E _ o }   ethernet@4,0smsc,lan9221smsc,lan9115*$  7*($U<f6F$ w* + E _ o }   target-module@480ab000ti,sysc-omap2ti,syscH H H revsyscsyss # fck+ H usb@0ti,omap3-musb\]{mcdma     M usb2-phy 2dss@48050000 ti,omap3-dssH Mdisabled dss_corefck+dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll Mdisabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH Mdisabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  Mdisabled dss_vencfckssi-controller@48058000 ti,omap3-ssissiMokayHHsysgddG{gdd_mpu+   ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+  >[defaulti hsusb2-2-pins0s   "  w3cbw003c-2-pinssisp@480bc000 ti,omap3-ispH H |  l ports+bandgap@48002524H%$ti,omap34xx-bandgap target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $sysc fck+ H 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'lis33-3v3-regregulator-fixedlis33-3v3-reg2Z2Zlis33-1v8-regregulator-fixedlis33-1v8-regw@w@regulator-vddvarioregulator-fixed vddvario 1regulator-vdd33aregulator-fixedvdd33a 1 compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellsphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypass#ssize-cellsti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columns#io-channel-cellsstatuspagesizeVdd-supplyVdd_IO-supplyst,click-single-xst,click-single-yst,click-single-zst,click-thresh-xst,click-thresh-yst,click-thresh-zst,irq1-clickst,irq2-clickst,wakeup-x-lost,wakeup-x-hist,wakeup-y-lost,wakeup-y-hist,wakeup-z-lost,wakeup-z-hist,min-limit-xst,min-limit-yst,min-limit-zst,max-limit-xst,max-limit-yst,max-limit-z#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csti,dual-voltpbias-supplyvmmc-supplybus-widthvqmmc-supplycap-sdio-irqnon-removable#iommu-cellsti,#tlb-entriesinterrupt-namesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinslinux,mtd-namenand-bus-widthgpmc,device-widthti,nand-ecc-optgpmc,sync-clk-psgpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,we-off-nsgpmc,oe-off-nsgpmc,access-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,wr-access-nsgpmc,wr-data-mux-bus-nslabelbank-widthgpmc,mux-add-datagpmc,oe-on-nsgpmc,we-on-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsenvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespoweriommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicepwmsmax-brightnesslinux,default-triggerti,modelti,mcbspgpiostartup-delay-usenable-active-highreset-gpiosvcc-supplyregulator-always-on