1. Input Files
2. Output Files
3. Log Files
4. Configuration Variables
5. Tcl Interface
6. Error Codes

Chapter 2 Subsections

2. Output Files
2. 1. VHDL - Generated Behavior
2. 1. 1. Description
2. 1. 2. Latches and Registers
2. 1. 3. High impedance or Conflictual Nodes
2. 1. 4. Vectorization
2. 1. 5. Example
2. 2. Verilog - Generated Behavior
2. 3. CNS - Cone Netlist Structure
2. 3. 1. Reason for CNS
2. 3. 2. CNS in Circuit Disassembly
2. 3. 3. CNS Terminology
The Global CNS Figure
A Cone and its Elements
Grouping of Cones
The CNS Figure Hierarchy
2. 4. CNS - Data Structures
2. 4. 1. The CNS Figure
2. 4. 2. The Link List
Link Structure Fields
Standard Link Types
2. 4. 3. The Branch List
Branch Structure Fields
Standard Branch Types
2. 4. 4. The Link List
Link Structure Fields
Standard Link Types
2. 4. 5. The Edge List
Edge Structure Fields
Standard Branch Types
2. 4. 6. The Transistor List
2. 4. 7. The Connector List
2. 4. 8. The Cell List
Cell Structure Fields
Standard Cell Types