The files and scripts needed for this example can be found in:
$AVT_TOOLS_DIR/tutorials/yagle/glitcher/ |
This example intends to illustrate the utility of timing back-annotating an abstracted behavioral model. In this lab, we are going to perform the abstraction of the glitcher design described below.
We will perform functional abstraction with and without timing back-annotation. We will see from simulation results of the behavioral models, that they do not present the same behavior. Actually, we will see that the zero-delay model simply doesn't work.
The glitcher design includes a delay cell (dly4x1), in order to render the path going through the signals Idly and IdlyN longer than the path going through the signals S0, S1, S2, S3, S4, S5. The operating timing diagram is then as follow:
The glitch on S6 is implied by the falling transition of I.
The zero-delay behavioral model is obtained by running the command:
> run.tcl |
Yagle generates the glitcher.vhd file. The result of the simulation is saved in the glitcher.vcd file, displayed in the following window.
The simulation of the zero-delay model makes the glitch on S6 appear at the rising transition of the input signal I, which is false.
The with-delay behavioral model is obtained by setting the variable yagleTasTiming to max.
To observe the glitch, it is necessary to have a second level precision. The variable yagleSplitTimingRatio is positioned to 1.
We can observe on the simulation trace (glitcher_timed.vcd) the correct behavior of the glitcher: the glitch is implied by the falling edge of I.