11. Hierarchical Analysis

11. 1. Design Description

This example illustrates the complete STA and SI of a hierarchical macro. It takes place in the h_macro/ directory.

The design is made up of two levels of hierarchy as in the following diagram:

The two low-level blocks adder and cpu2901 are full-custom blocks (analyzed in the preceding examples), designed at transistor-level, and extracted as flat transistor net-lists with parasitics (including coupling capacitances).

The ram4x128 is an abstracted model of a 128-4bit-word memory.

The top-level instantiates these three blocks, and is back-annotated with parasitics (including coupling capacitances).

11. 2. Database Generation

11. 2. 1. Global Configuration

The complete configuration required for the database generation takes place in the db.tcl. The script also launches the commands that effectively generate that database.

avt_config avtLibraryDirs ".:../lab3_adder:../lab6_cpu"
tells the tool where to find timing databases for the lower levels of hierarchy.
avt_config avtVddName vdd
tells the tool which signal must be considered as a power supply, necessary as netlist is not spice.
avt_config avtVssName vss
idem for ground signal identification.
avt_config tasHierarchicalMode yes
tells the tool to work hierarchically.
avt_LoadFile ./ram4x128.lib lib
load the abstracted block ram4x128.lib
avt_LoadFile top.v verilog
load the Verilog netlist of top
avt_LoadFile top.spef spef
load the parasitics back-annotation in SPEF format

11. 2. 2. Database Generation

The generation launch is done through the command hitas:

set fig [hitas top] 

11. 3. Database Analysis

11. 3. 1. Path Searching with the Tcl Interface

The complete configuration required for the database browsing takes place in the report.tcl.

The command:

set fig [ttv_LoadSpecifiedTimingFigure top]

reads the timing database from disk.

The command:

set clist [ttv_GetPaths $fig * * uu 5 critic path max]

gives the 5 critical paths of the design.

The command:

ttv_DisplayPathListDetail stdout $clist

displays on the standard output the detail of all the paths of the path list given by the ttv_GetPaths function.

11. 4. Timing Checks

The complete configuration required for stability analysis takes place in the sta.tcl.

11. 4. 1. Timing Constraints

Timing constraints are set in SDC format. For this example we use the same constraints specified for the cpu2901 example.

11. 4. 2. STA

Launch of the static timing analysis is done by invoking the following commands:

As before, the command:

set fig [ttv_LoadSpecifiedTimingFigure top]

reads the timing database from disk.

The command:

set stbfig [stb $fig]

launches the STA

The function:

stb_DisplaySlackReport [fopen slack.rep w] $fig * * ?? 10  all 10000

displays a global slack report in the file slack.rep.