The tutorial and the related files can be found in the following directory:
$AVT_TOOLS_DIR/tutorials/yagle |
Among the directories presents in $AVT_TOOLS_DIR/tutorials/yagle, this tutorial will use the following ones:
Along the tutorial the user is expected to change directory as needed to perform the operations related to each specific example.
The technology file used during the course of the tutorial is bsim4_dummy.hsp located in:
$AVT_TOOLS_DIR/tutorials/techno/bsim4_dummy.hsp |
Yagle is an automatic transistor-to-RTL functional abstractor, which automatically handles any kind of digital circuitry (CMOS and NMOS, pass-transistor logic, transmission gate logic, dynamic logic) and automatically detects and models latches and registers. Yagle generates industry-standard VHDL or Verilog, with a Spice-accurate timing back-annotation.
Yagle integrates in the most common design flows, as illustrated in the following diagram:
The netlist can be fed into Yagle in various formats, at different levels of hierarchy:
Yagle functionalities are provided through a set of functions, that can be accessed through Avertec's Tcl interface: avt_shell.
Tool configuration is done with variables. The value of each variable can be set in the Tcl script by the avt_config function.
Yagle generates the following output files:
The XYagle GUI is invoked in the following way:
> xyagle & |
XYagle is mainly used to browse the CNS intermediate disassembled netlist. For further information, please refer to the Yagle reference manual.