avtVddName |
|
<string> |
Name of any signal or connector which is to be considered as power supply (a * in the name matches any string). Several names, separated by :, may be specified.
|
|
avtVssName |
|
<string> |
Name of any signal or connector which is to be considered as ground (a * in the name matches any string). Several names, separated by :, may be specified.
|
|
avtGlobalVddName |
|
<string> |
Name of an internal signal to be considered as power supply (a * in the name matches any string). Signals in different subcircuits of a hierarchical
netlist with a name given here will be considered as equipotential and this name will
be used in the flattened netlist. This is identical to the use of the .GLOBAL directive
in a spice netlist. Several names, separated by :, may be specified.
|
|
avtGlobalVssName |
|
<string> |
Name of an internal signal to be considered as ground (a * in the name matches any string). Signals in different subcircuits of a hierarchical
netlist with a name given here will be considered as equipotential and this name will
be used in the flattened netlist. This is identical to the use of the .GLOBAL directive
in a spice netlist. Several names, separated by :, may be specified.
|
|
avtCaseSensitive |
|
yes |
Upper and lower case characters are distinct |
no |
Upper and lower case characters are seen as identical |
preserve |
Default, upper and lower case characters are seen as
identical but the original case is preserved
|
|
avtInstanceSeparator |
|
<char> |
Character used to separate instance names in a hierarchical description. Default value
is . |
|
avtFlattenKeepsAllSignalNames |
|
yes |
When flattening a netlist, each signal keeps all its
names through the hierarchy.
|
no |
Default, only one name (the shortest) is kept per signal. |
|
avtVectorize |
|
Controls the internal representation of vector-signals.
yes |
Default, vector-signals are represented internally as vectors,
as far as the vector indexation is one of [], <>, _. For example, if both foo[1],
foo<1> and foo_1 appear in the source file, they will all be represented internally
as foo 1 |
no |
Vector signals are represented internally as they appear in the
source file.
|
<string> |
Explicits the vector-signals indexations that will
be interpreted as vectors, and the represented internally as vectors. string is a
comma-separated list of single or paired delimiters. For example, if string is set to "[],_",
only foo[1] and foo_1 will be represented internally as foo 1.
|
Special attention should be paid to the Verilog case. Verilog only accepts [] as legal
vector indexation. Legal verilog vectors are represented internally as vectors if
avtVectorize is
different to no.
Illegal Verilog vectors are supported and controlled by avtVectorize as far as they are escaped
and avtStructuralVerilogVectors is set to yes. For example, \foo<1> is represented
internally as a vector if avtStructuralVerilogVectors is set to yes and avtVectorize is
set to <>.
|
fclLibraryName |
|
<string> |
Name of the file containing the list of cells in
the user-defined cell library used. The default is LIBRARY.
|
|
fclLibraryDir |
|
<string> |
Access path to the directory containing the user-defined cell
library used. Default is a directory /cells in avtWorkDir.
|
|
fclGenericNMOS |
|
<string> |
A colon separated list of transistor model names which
the FCL pattern-matching engine considers will match to any N-type transistor. If
a pattern netlist contains non-generic
N-channel transistors then these transistors will only match to transistors with an
identical model.
Default is tn:TN.
|
|
fclGenericPMOS |
|
<string> |
A colon separated list of transistor model names which
the FCL pattern-matching engine considers will match to any PMOS transistor. If a
pattern netlist contains non-generic
P-channel transistors then these transistors will only match to transistors with an
identical model.
Default is tp:TP.
|
|
fclWriteReport |
|
yes |
A correspondence file is created if the -fcl option is used.
This file details all the recognized instances.
|
no |
Default |
|
fclAllowSharing |
|
yes |
Matched cells are allowed to share transistors. |
no |
Default |
|
fclCutMatchedTransistors |
|
yes |
Matched transistors are eliminated from the transistor netlist.
Results in a strict partitioning of the cones and the matched cells.
|
no |
Default |
|
fclMatchSizeTolerance |
|
<int> |
Percentage tolerance for matching transistor sizes. |
|
fclTraceLevel |
|
<int> |
Number greater than 0. Trace information is displayed during
the pattern-matching phase.
|
|
fclDebugMode |
|
<int> |
Number greater than 0. Additional debugging information is
displayed during the pattern-matching phase.
|
|
gnsLibraryName |
|
<string> |
Name of the file (recognition library) containing the list of cells
to recognize. Default is LIBRARY.
|
|
gnsLibraryDir |
|
<string> |
Access path to the directory containing the recognition library.
Default is directory cells/ in avtWorkDir.
|
|
gnsKeepAllCells |
|
yes |
All matched structures are extracted from the netlist. |
no |
Default |
|
gnsTemplateDir |
|
<string> |
Directory where to find the GNS templates.
Default is $AVT_TOOLS_DIR/gns_templates.
|
|
gnsTraceLevel |
|
<int> |
From 0 to 6. Indicates the level of trace displayed during
the recognition phase. Default is 0.
|
|
gnsTraceFile |
|
<string> |
Name of the output trace file. Default is stdout. |
|
gnsTraceModel |
|
<string> |
When tracing the recognition, indicates the name
of the recognized model to trace. If not specified, traces all models.
|
|
gnsFlags |
|
This configuration controls the behavior of GNS. The values (flags) are added separated
with commas. Available flags are:
EnableCore |
Enable the generation of a core file for a crash in a user compiled API. |
NoGns |
Disables the generation of the .gns file
|
VerboseGns |
Produces a more readable .gns file.
|
NoOrdering |
Disables the top-level instance connectors reordering.
Should not be set if using the BEG functions.
|
|