Package: cocotb Version: 1.2.0-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 1279 Depends: python Filename: ./i386/cocotb_1.2.0-c4m.0.0_i386.deb Size: 199830 MD5sum: 447f842924e604b4cc1c35338dae7658 SHA1: 7ccda9341f45ccf1700e262e4b4c0e5d8565a39f SHA256: a3025ce2f0883e84e7a18a3f59f735ff3943d27edaa048ae4d36eff031d2a952 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: cocotb Version: 1.2.0-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1279 Depends: python Filename: ./amd64/cocotb_1.2.0-c4m.0.0_amd64.deb Size: 199956 MD5sum: c1eb4337fa25944a1cdfa2e9fd546103 SHA1: df21e180aea58deb85e93d8eb1e0a23a9c79f0f3 SHA256: 61d14e83c3e504495c0e4adcb57a3d0163747a85d664870472173d8b5cc4252d Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: graywolf Version: 0.1.6.191014-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 1111 Depends: libc6 (>= 2.7), libgsl2, libx11-6 Filename: ./i386/graywolf_0.1.6.191014-c4m.0.0_i386.deb Size: 401744 MD5sum: 9b9248d9030780a942dc176542a413e9 SHA1: 5d9547367e8c5904ea28b9b3cac16260149e4693 SHA256: 30f61f416f7e19e9227703d7975ada2bbe762bb212f67213e479977bdd806af7 Section: electronics Priority: extra Description: Standard cell placer forked from TimberWolf graywolf is used for placement in VLSI design. It's mainly used together with qflow. . http://opencircuitdesign.com/qflow/ Package: graywolf Version: 0.1.6.191014-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1138 Depends: libc6 (>= 2.7), libgsl2, libx11-6 Filename: ./amd64/graywolf_0.1.6.191014-c4m.0.0_amd64.deb Size: 409576 MD5sum: 0dd19f4ab8e4dd987529980e4f108465 SHA1: e37e46bddf393d2d61b15a98866f630d0a19b2bf SHA256: 05f5a2038fd786cbb9e9a813c6c42d9d9ce61906f253a6e34fb6445639da3ad6 Section: electronics Priority: extra Description: Standard cell placer forked from TimberWolf graywolf is used for placement in VLSI design. It's mainly used together with qflow. . http://opencircuitdesign.com/qflow/ Package: gtkwave Version: 3.3.103.dev.r1543-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 4423 Depends: libbz2-1.0, libc6 (>= 2.11), libcairo2 (>= 1.2.4), libgcc1 (>= 1:4.2), libgdk-pixbuf2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.12.0), libgtk2.0-0 (>= 2.24.0), liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./i386/gtkwave_3.3.103.dev.r1543-c4m.0.0_i386.deb Size: 2377604 MD5sum: 078befb41b2b10067092abb591501860 SHA1: 5726e96da1424ae13668f37c6a02912459e189a8 SHA256: 893575dc5579126a58181141e3e1e07ab6e6f773b35bcb3627f5b0265c4cdd9d Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools. Package: gtkwave Version: 3.3.103.dev.r1543-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 4290 Depends: libbz2-1.0, libc6 (>= 2.14), libcairo2 (>= 1.2.4), libgcc1 (>= 1:3.0), libgdk-pixbuf2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.12.0), libgtk2.0-0 (>= 2.24.0), liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/gtkwave_3.3.103.dev.r1543-c4m.0.0_amd64.deb Size: 2344386 MD5sum: 5c928e36a65309a60d19ffd1aeba3786 SHA1: f58cc06104d51974db56df929053bf6f17102549 SHA256: 39af42d25934d39219e93a9934a6c09f5dc2948788df8ee32578789ce8e6852d Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a waveform viewer that can view VCD files produced by most Verilog simulation tools, as well as LXT files produced by certain Verilog simulation tools. Package: iverilog Version: 11.0.dev20191104.gita621fa4-c4m.0.0 Architecture: i386 Maintainer: Chips4Makers Installed-Size: 7 Filename: ./i386/iverilog_11.0.dev20191104.gita621fa4-c4m.0.0_i386.deb Size: 1122 MD5sum: 2f07f515afc6af847de6c73a453c23eb SHA1: c95fa8c9aa7a9ae483a365d280eb7f741aeb8d45 SHA256: 03b86782b7eaefbe9ae88f6af8c59e15b3db8445cfa84c574f5066e7b3669b7d Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. Package: iverilog Version: 11.0.dev20191104.gita621fa4-c4m.0.0 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 7 Filename: ./amd64/iverilog_11.0.dev20191104.gita621fa4-c4m.0.0_amd64.deb Size: 1122 MD5sum: 0e4c0fde0532cea5ca38a556f2dfbdf8 SHA1: 67cd795d6a7a0ea92f5b86e52b2ed89d3eebe100 SHA256: bf4e977e78eeb804f4ae9b0cf369fbe3a2af601dea812fa8c7268fecaffcf782 Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard. Package: magic Version: 8.2.144-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 2616 Depends: libc6 (>= 2.0), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0) Filename: ./i386/magic_8.2.144-c4m.0.0_i386.deb Size: 966086 MD5sum: bb382279566c09d3b67d4d15595dad89 SHA1: 6f827ca1b953969c830c2564ac0c752d544e22f9 SHA256: ae94210a52e06a24aada19bf49a942f8242ce2ce476001b37103599ba87600da Section: electronics Priority: extra Description: Magic detail router for digital ASIC designs Magic detail router for digital ASIC designs . http://opencircuitdesign.com/magic/ Package: magic Version: 8.2.144-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 2618 Depends: libc6 (>= 2.2.5), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0) Filename: ./amd64/magic_8.2.144-c4m.0.0_amd64.deb Size: 967710 MD5sum: 22c5ab1a7e0b06b37c495f303058a8fe SHA1: 9dfd72fe3a86961a30d61a90cb1c23886c0f0a5d SHA256: 8a98a46a119140fe3779f025e485c87c2d3c2ca008e5891bf7c20d01c8569239 Section: electronics Priority: extra Description: Magic detail router for digital ASIC designs Magic detail router for digital ASIC designs . http://opencircuitdesign.com/magic/ Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 707 Depends: libc6 (>= 2.7), libtcl8.6 (>= 8.6.0) Filename: ./i386/netgen-lvs_1.5.133-c4m.0.0_i386.deb Size: 178402 MD5sum: 9db844997058bea92f8da87eafce43f1 SHA1: 8b019ce3227ee9ceb04ffdfbc8acd7494efe91fb SHA256: 72d3ea786e4d8c9a3c96adc7a96221be56c3118ce825ed9807eee8e190076854 Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 737 Depends: libc6 (>= 2.14), libtcl8.6 (>= 8.6.0) Filename: ./amd64/netgen-lvs_1.5.133-c4m.0.0_amd64.deb Size: 191492 MD5sum: 971ed574ed68eb7816ce48b26bf0106b SHA1: 18456e1b8237f93eebe750db327b94365e808bc9 SHA256: 7995af849b0efcd04d3de0207040a8b87898bb1cde590611bc975c4cd8b8d205 Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: qflow Version: 1.4.62-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 5709 Depends: libc6 (>= 2.7), yosys, graywolf, qrouter, magic, netgen-lvs Conflicts: qflow-tech-osu018, qflow-tech-osu035, qflow-tech-osu050 Filename: ./i386/qflow_1.4.62-c4m.0.0_i386.deb Size: 582762 MD5sum: 42a190fb6d1a20fce6881ea9fb007ceb SHA1: 94cd7aabd228ffee15d989b2c5a88b48bffde118 SHA256: aeb006862e553852125b989944b1303857a88a6c7734956d6dc38df5ffeb9b0b Section: electronics Priority: extra Description: Qflow full end-to-end digital synthesis flow for ASIC designs Qflow full end-to-end digital synthesis flow for ASIC designs . http://opencircuitdesign.com/qflow/ Package: qflow Version: 1.4.62-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 5645 Depends: libc6 (>= 2.14), yosys, graywolf, qrouter, magic, netgen-lvs Conflicts: qflow-tech-osu018, qflow-tech-osu035, qflow-tech-osu050 Filename: ./amd64/qflow_1.4.62-c4m.0.0_amd64.deb Size: 577868 MD5sum: ec02eb9c00c21b0fbb46ac64c54517c4 SHA1: b46fcd0e6e6a8963e69b4a81f5e5a4974649f5dc SHA256: 5e78c9c3d16710dc177093b59e09166944fc9f8086ad1f8afc9fd9fb2b37c0c2 Section: electronics Priority: extra Description: Qflow full end-to-end digital synthesis flow for ASIC designs Qflow full end-to-end digital synthesis flow for ASIC designs . http://opencircuitdesign.com/qflow/ Package: qrouter Version: 1.4.19-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 503 Depends: libc6 (>= 2.7), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), libx11-6 Filename: ./i386/qrouter_1.4.19-c4m.0.0_i386.deb Size: 170380 MD5sum: 2aa487b57c8e0b7d7359d89d0055c5c6 SHA1: 633be658a79e5bf25196c38dad53f43ef23ba46e SHA256: 1e4538a8b3882e7f55d1abd6f852cabb4d32df76813b339834b0e86238c59092 Section: electronics Priority: extra Description: Qrouter detail router for digital ASIC designs Qrouter detail router for digital ASIC designs . http://opencircuitdesign.com/qrouter/ Package: qrouter Version: 1.4.19-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 479 Depends: libc6 (>= 2.14), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), libx11-6 Filename: ./amd64/qrouter_1.4.19-c4m.0.0_amd64.deb Size: 164948 MD5sum: 5888aaeb519a141211b111c1ee1f91ab SHA1: cc3271ca5112fafb130a3134324c5103f4803191 SHA256: 19db29d6414b1336e2068ba9d35be0967c5b4fd2e79982fb56b1ae89720ebda6 Section: electronics Priority: extra Description: Qrouter detail router for digital ASIC designs Qrouter detail router for digital ASIC designs . http://opencircuitdesign.com/qrouter/ Package: verilator Version: 4.020-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 11235 Depends: libc6 (>= 2.4), libgcc1 (>= 1:4.2), libstdc++6 (>= 5.2) Filename: ./i386/verilator_4.020-c4m.0.0_i386.deb Size: 2757664 MD5sum: 5b2358168e34c43b08e1d97d2451af2f SHA1: d19842cb665026b91a479f0ae1d58c1dd5a18d4b SHA256: 40bac741133db364cf6d39fef058828fce7ba5d01bae521307f34b50b86ff672 Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: verilator Version: 4.020-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 11632 Depends: libc6 (>= 2.14), libgcc1 (>= 1:3.0), libstdc++6 (>= 5.2) Filename: ./amd64/verilator_4.020-c4m.0.0_amd64.deb Size: 2693734 MD5sum: cdd241905100a6d8ae8d0a3e21f6e4ac SHA1: 27ec54b09826baab2a8f7aa0520dbdc148989e48 SHA256: 6ab81344ae4be12b17fa1815894f97cac0c1ea0dc0fe6d6d815e2a140f6547cf Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: yosys Version: 0.9+932-c4m.0.0 Architecture: i386 Maintainer: Staf Verhaegen Installed-Size: 46244 Depends: libc6 (>= 2.15), libffi6 (>= 3.0.4), libgcc1 (>= 1:3.0), libreadline6 (>= 6.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./i386/yosys_0.9+932-c4m.0.0_i386.deb Size: 12660704 MD5sum: 47c22ab76a5529323c3c188b423d7386 SHA1: 0d32a4e067605b362b32bc3e583446a27b1ec893 SHA256: 2143df8ddf17edb4726671e0bc01ccb81f35138061037e9d472cf5df1638d2c5 Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/ Package: yosys Version: 0.9+932-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 43209 Depends: libc6 (>= 2.15), libffi6 (>= 3.0.4), libgcc1 (>= 1:3.0), libreadline6 (>= 6.0), libstdc++6 (>= 5.2), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/yosys_0.9+932-c4m.0.0_amd64.deb Size: 12075736 MD5sum: 7ef0574af8c84e821c11978c896a6f26 SHA1: 742c3e3d4a77f3a0ea583aab79d6e65b7b0b9dc2 SHA256: 1b1472cee3f000aa1f99203c42c003f13d18604e366c11941bb1b6d0928b9ee3 Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/