Package: cocotb Version: 1.5.2-c4m.1+6.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1999 Depends: libc6 (>= 2.34), libgcc-s1 (>= 3.3.1), libstdc++6 (>= 11), python Filename: ./amd64/cocotb_1.5.2-c4m.1+6.1_amd64.deb Size: 313902 MD5sum: 0cdd594205c80b8db027937a0def239a SHA1: 34eb3b3de9bf6847f4138705dcec4a6e6a467cef SHA256: 4251bc2ef23154382ac060d765c169c03cb59564f1f0bd94529b65981b775361 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: ghdl Version: 1.0.1.dev20210706.git1285cbf-c4m.1+4.1 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 20019 Depends: libc6 (>= 2.34), libgcc-s1 (>= 3.0), libgnat-11 (>= 11.2.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/ghdl_1.0.1.dev20210706.git1285cbf-c4m.1+4.1_amd64.deb Size: 3345846 MD5sum: f1ade74dfef9a193265699fd615dc771 SHA1: 728f6eb170919317d7d540d5d78d762dce65914f SHA256: df35aac2d7ed4d3cd41088c7168b93d626d25d86c4aa9eca5c4d5e700bebb1a6 Section: electronics Priority: extra Description: GHDL GHDL is the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language. GHDL is not an interpreter: it allows you to analyse and elaborate sources for generating machine code from your design. Native program execution is the only way for high speed simulation. Package: ghdl-yosys-plugin Version: 0.0.0.dev20210327.git5fad8b9-c4m.1+3.3 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 145 Depends: ghdl, yosys Filename: ./amd64/ghdl-yosys-plugin_0.0.0.dev20210327.git5fad8b9-c4m.1+3.3_amd64.deb Size: 39178 MD5sum: 6328c946bd2051f49bdc394c55a2a43f SHA1: 17a84574479aa55cead1f12f44595b767cc153df SHA256: 7397acddc9f117dcfa23ec9bde2fab6b09bca1bd5443d3a82a328f9cda326e9d Section: electronics Priority: extra Description: VHDL synthesis VHDL synthesis (based on GHDL and Yosys) Package: gtkwave Version: 3.3.110-c4m.1+3.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 4628 Depends: libbz2-1.0, libc6 (>= 2.34), libcairo2 (>= 1.10.0), libgcc-s1 (>= 3.0), libgdk-pixbuf-2.0-0 (>= 2.22.0), libglib2.0-0 (>= 2.49.3), libgtk-3-0 (>= 3.21.5), libjudydebian1, liblzma5 (>= 5.1.1alpha+20120614), libpango-1.0-0 (>= 1.14.0), libpangocairo-1.0-0 (>= 1.14.0), libstdc++6 (>= 11), libtcl8.6 (>= 8.6.0), libtk8.6 (>= 8.6.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/gtkwave_3.3.110-c4m.1+3.1_amd64.deb Size: 2472076 MD5sum: 2e17b1f5dd9078d257742da38739d747 SHA1: e936c2823db73b99dbd0cc224d45aba575239935 SHA256: fdcf0ce2309c541bffb9f3d7609e8975eb58d4be85fb9098f06cf38ff6d5e4b2 Section: electronics Priority: extra Description: Waveform Viewer GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing. Package: klayout Version: 0.27.2-c4m.1+5.1 Architecture: amd64 Maintainer: Matthias Köfferlein Installed-Size: 191796 Depends: libc6 (>= 2.34), libgcc-s1 (>= 3.0), libpython3.10 (>= 3.10.0), libqt5core5a (>= 5.15.1), libqt5designer5 (>= 5.6.0~beta), libqt5gui5 (>= 5.14.1) | libqt5gui5-gles (>= 5.14.1), libqt5multimedia5 (>= 5.6.0~beta), libqt5multimediawidgets5 (>= 5.6.0~beta), libqt5network5 (>= 5.14.1), libqt5printsupport5 (>= 5.4.0), libqt5sql5 (>= 5.10.0), libqt5svg5 (>= 5.6.0~beta), libqt5widgets5 (>= 5.15.1), libqt5xml5 (>= 5.1.0), libqt5xmlpatterns5 (>= 5.9.0), libruby3.0 (>= 3.0.0~preview1), libstdc++6 (>= 11), zlib1g (>= 1:1.1.4) Filename: ./amd64/klayout_0.27.2-c4m.1+5.1_amd64.deb Size: 39495422 MD5sum: 5f1354d1ffddf226959cb62f23edc838 SHA1: b40389e9911b0f55e96d854b71919cd9993cfe97 SHA256: 3f10d0535e1fca427ce2f4b286db2ed8566faed875cd93553b3a27b887ca43f7 Section: electronics Priority: optional Description: Chip mask layout review and edit utility Klayout is a graphical viewer and editor for a.o. GDSII, OASIS, CIF and other files. Its features include net highlighting and XOR-ing of two layouts, scripting capabilities in Ruby and Python and much more. Package: netgen-lvs Source: netgen Version: 1.5.133-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 761 Depends: libc6 (>= 2.34), libtcl8.6 (>= 8.6.0) Filename: ./amd64/netgen-lvs_1.5.133-c4m.0.0_amd64.deb Size: 203596 MD5sum: da22b3ac7040d5bba9e0b285c2d02b43 SHA1: 61a346fde7aa7f0c1785cb09311911960c521d44 SHA256: c923c3578c21175185b315d5aca2665cf61ca66e495757e3f530469423461335 Section: electronics Priority: extra Description: Netgen complete LVS tool for comparing SPICE or verilog netlists Netgen complete LVS tool for comparing SPICE or verilog netlists . http://opencircuitdesign.com/netgen/ Package: opensta Version: 2.2.1.dev20210719.git37cd1fc-c4m.0.0 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 12453 Depends: libc6 (>= 2.34), libgcc-s1 (>= 3.0), libstdc++6 (>= 12), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/opensta_2.2.1.dev20210719.git37cd1fc-c4m.0.0_amd64.deb Size: 1871614 MD5sum: 7bae36d8748810e744b5eccd5e1f6e10 SHA1: 23aaebc22f9e51dc8eb778e783fe76c858819301 SHA256: 7c8aaabfdc36f4b772b1da88d8029762b0825d141cc48222b3ab636af91139fc Section: electronics Priority: extra Description: OpenSTA is a gate level static timing verifier Package: verilator Version: 4.106-c4m.1+6.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 19823 Depends: zlib1g-dev, libc6 (>= 2.35) Filename: ./amd64/verilator_4.106-c4m.1+6.1_amd64.deb Size: 4745808 MD5sum: 7ce8e97c376ca3fe6a90de07b1b8ae13 SHA1: 9e3059b6eb1ace65259a3676c3846d08fe159b67 SHA256: 7a608291969b72723d36921b6c5197c6a76a13da127e175049ef86b99f1efd6e Section: electronics Priority: extra Description: A fast simulator for synthesizable Verilog Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Package: yosys Version: 0.9+4081-c4m.1+6.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 37826 Depends: libc6 (>= 2.35), libffi8 (>= 3.4), libgcc-s1 (>= 3.0), libreadline8 (>= 6.0), libstdc++6 (>= 11), libtcl8.6 (>= 8.6.0), zlib1g (>= 1:1.1.4) Filename: ./amd64/yosys_0.9+4081-c4m.1+6.1_amd64.deb Size: 11601904 MD5sum: f4707f86bf181efe1283f56f77a12243 SHA1: c7b791b5254e97bbf4794bbe03d2f20d4f2b2c68 SHA256: b5386ae8ee9742c8d2faf995fc488e1c30e6aa4c0ca37c038d7823407a89d416 Section: electronics Priority: extra Description: Yosys Open SYnthesis Suite This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license). . http://www.clifford.at/yosys/