Package: cocotb Version: 1.5.2-c4m.1+7.1 Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1947 Depends: libc6 (>= 2.14), libgcc1 (>= 1:3.3.1), libstdc++6 (>= 5.2), python Filename: ./amd64/cocotb_1.5.2-c4m.1+7.1_amd64.deb Size: 283124 MD5sum: 973897e5e2b29c70a5b6156345b63ba9 SHA1: 30d6fdfa75bea1b1ae918a08331384795ff5cdc2 SHA256: 17791335ff1f64c7f16ca8bc482f472d66c27ddd0ff9ef0932b3f62e26e00ac7 Section: electronics Priority: extra Description: COroutine based COsimulation TestBench cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. . cocotb is completely free, open source (under the BSD License) and hosted on GitHub. . cocotb requires a simulator to simulate the RTL. Simulators that have been tested and known to work with cocotb: . Linux Platforms * Icarus Verilog * GHDL * Aldec Riviera-PRO * Synopsys VCS * Cadence Incisive * Mentor ModelSim (DE and SE) . Windows Platform * Icarus Verilog * Aldec Riviera-PRO * Mentor ModelSim (DE and SE) . https://cocotb.readthedocs.io Package: cocotb-dbgsym Source: cocotb Version: 1.5.2-c4m.1+7.1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 1768 Depends: cocotb (= 1.5.2-c4m.1+7.1) Filename: ./amd64/cocotb-dbgsym_1.5.2-c4m.1+7.1_amd64.deb Size: 1243720 MD5sum: 8ba478229cc5f2d75546a4fc3fa667d7 SHA1: 7bfb417115fe97c732f68e6687bba8855a2a33a6 SHA256: da4d2059357211939dd90473b2c1122868325c1112bcf2a5dfce2ded8ad9771c Section: debug Priority: optional Description: debug symbols for cocotb Build-Ids: 1de5cd4f00ec53055d41b7db4015e4ba22850c2f 398b26f96ceb16039140c091f03c1f111f35e643 78b4f2a34460fda189c3f08acac5e200e887caf0 7e50579328115484c6ab096fbbdcdd1b9f218c0c 7f8ce289ead9217de3124e4f3195cd5c6a28b99e b18e83013eb03d0b005ece5840ddf81a955063dc b56cc8afdf1a09f00edd2530e211062d0eed0bf5 b78339a239b549a3fb0a08539cf2eb0684a70aa8 b85c0d0be327223b7257c8bee13975a259ac3f73 c56a1e7691b2814cd02aaf385f5169d791ea5148 e1ef8ec7686b1f3fa8e641985ddadb527fcf4097 e54b45954f80ba1be7829b91bb32b1d68ee154fd fe3760f604c90506d620c2db918917f916f7c69a Package: ghdl Version: 1.0.1.dev20210706.git1285cbf-c4m.1+5.1 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 20228 Depends: libc6 (>= 2.14), libgcc1 (>= 1:3.0), libgnat-8 (>= 8.3.0), zlib1g (>= 1:1.2.0) Filename: ./amd64/ghdl_1.0.1.dev20210706.git1285cbf-c4m.1+5.1_amd64.deb Size: 3029188 MD5sum: 116cdff56a796dfe901b5effde7c9368 SHA1: 81f81c53f4fd7cf99025e66b7ad411282d5e2073 SHA256: 83c360b153db1c0c7e6249fc2902a5c3c33d73506d1a31977d78c4aee4c2bc9d Section: electronics Priority: extra Description: GHDL GHDL is the open-source analyzer, compiler, simulator and (experimental) synthesizer for VHDL, a Hardware Description Language. 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Package: gtkwave-dbgsym Source: gtkwave Version: 3.3.110-c4m.1+4.1 Auto-Built-Package: debug-symbols Architecture: amd64 Maintainer: Staf Verhaegen Installed-Size: 6024 Depends: gtkwave (= 3.3.110-c4m.1+4.1) Filename: ./amd64/gtkwave-dbgsym_3.3.110-c4m.1+4.1_amd64.deb Size: 5829436 MD5sum: 35c3b1f155692427ecaf396fd49139ae SHA1: cb5afdff15d169934d683019fd2c425b0df6933c SHA256: b8d3556190b3052e199f758613479af132f490d4947df124d42b01c4ba75731f Section: debug Priority: optional Description: debug symbols for gtkwave Build-Ids: 1fe0260291f805f66d130b7dd7dfa529413df1c9 2a9707254f8f6ef8f0c02118a25d1e49991535d8 2d9311b10201dbd541692f13afe6e77f85b1a13a 4a68c1a1d63da985ccb59628b02fdafe5ca052a9 4d3c1a508d1d13c44e26b6424069a1caf3acad59 5918e524eab1d78336dc476fee1b92cded571ed4 59268a3ae500eed087e6ac57d69922b231498598 82aa2feaa79791af307d6c7a2081d596dc24b528 a05fc3d4d185afe8700e2a78aefd1db14e812f93 a77b5238206434b7b4c013c7ceede6a1e7f56105 afffe2c4162d1fa155647b87423fd153c283c5e1 b1c6bb083744d7b1fb2dc5eaf492e6b5531b17cd c988208790d5ee26465568ef5ea322bc1186abdc da699b26c48e679c9a79576ac403e01c04f5b687 dfc3fda71d06368e8f3a7c4cb441e4d2d37799ab f325adfe5c2c912e818eb7198d74b06e650c1b29 Package: iverilog Version: 11.0-c4m.1+5.1 Architecture: amd64 Maintainer: Chips4Makers Installed-Size: 6571 Depends: libc6 (>= 2.14), libgcc1 (>= 1:3.0), libreadline7 (>= 6.0), libstdc++6 (>= 5.2), libtinfo6 (>= 6), zlib1g (>= 1:1.2.0) Filename: ./amd64/iverilog_11.0-c4m.1+5.1_amd64.deb Size: 1909096 MD5sum: c77989a024ad89326f7c501dd9003aba SHA1: 1afa77beae3df314f45f5fe7e04075475390070b SHA256: 7c3a964153d7ac93284a39b8aeb6d9b71aa8142261fb489659a85f961347a078 Section: electronics Priority: extra Description: Icarus Verilog Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. 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It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains. . Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base. . 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